Mail Index

• Thread Index

• [oc] ATA-3 or General ATA Questions
  • From: "Morris, Scott J" <morris.scott@pnl.gov>
• [oc] Timing tool
  • From: Jamil Khatib <khatib@ieee.org>
• [oc] Pulse width discriminator
  • From: "Golnaz Vahedi" <golnaz2120@hotmail.com>
• [oc] firewire info
  • From: "anupama toshniwal" <anupamat@hotmail.com>
• [oc] Increase business with wealthy Russian clients
  • From: "MOSCOW WORKSHOPS" <moscowworkshops@email.com>
• [oc] Contributing to an existing project
  • From: Victor Snesarev <vnsnes@yahoo.com>
• [oc] UART16550 core
  • From: "Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>
• [oc] VHDL in SYNOPSYS
  • From: rmmy@ee.iitb.ac.in
• [oc] (sans sujet)
  • From: XGuillot@aol.com
• [oc] WISHBONE DMA and Memory Controller
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] operation systems from partitions,
  • From: Maria Teresa <treyes@prodigy.net.mx>
• [oc] Tell a Friend about Best50-India
  • From: <best50@india.com>
• Re: [oc] question regarding vhdl
  • From: "Johnsonw10" <johnsonw10@hotmail.com>
• [oc] administration
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [oc] OR1k CPU
  • From: "Damjan Lampret" <lampret@opencores.org>
• [oc] OR1k CPU
  • From: Jamil Khatib <khatib@ieee.org>
• [oc] Successful Compiles of the ATA-3 Core
  • From: Jim Kjendalen <jimkje@adaptivemicro.com>
• RE: [oc] bidirection pin on acex 1k30 from Altera
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] Configuration Bit Stream Generators
  • From: Marko Mlinar <marko.mlinar@flextronicssemi.com>
• Re: [oc] Configuration Bit Stream Generators
  • From: Marko Mlinar <marko.mlinar@flextronicssemi.com>
• Re: [oc] Re: PCI Linux driver
  • From: "Miha Dolenc" <miha@iprom.si>
• RE: [oc] bidirection pin on acex 1k30 from Altera
  • From: Daniel Haensse <daniel.haensse@alumni.ethz.ch>
• Re: [oc] Configuration Bit Stream Generators
  • From: Victor the Cleaner <jonathan@canuck.com>
• [oc] Re: PCI Linux driver
  • From: Andreas Bombe <andreas.bombe@munich.netsurf.de>
• Re: [oc] Configuration Bit Stream Generators
  • From: "Jamie Morken" <jmorken@home.com>
• RE: [oc] bidirection pin on acex 1k30 from Altera
  • From: "Olson, Gary" <GOlson@armillaire.com>
• Re: [oc] Configuration Bit Stream Generators
  • From: "Dave Feustel" <dfeustel@mindspring.com>
• RE: [oc] bidirection pin on acex 1k30 from Altera
  • From: Jim Kjendalen <jimkje@adaptivemicro.com>
• Re: [oc] Configuration Bit Stream Generators
  • From: John William Dalton <jdalton@asiaonline.net.au>
• Re: [oc] Configuration Bit Stream Generators
  • From: Juan José "Peco" San Martín <peco@microbotica.es>
• Re: [oc] Configuration Bit Stream Generators
  • From: Juan José "Peco" San Martín <peco@microbotica.es>
• Re: [oc] Configuration Bit Stream Generators
  • From: Marko Mlinar <marko.mlinar@flextronicssemi.com>
• [oc] PCI Linux driver
  • From: "Miha Dolenc" <mihad@opencores.org>
• [oc] WISHBONE Simulation Models
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Configuration Bit Stream Generators
  • From: "Dave Feustel" <dfeustel@mindspring.com>
• Re: [oc] Configuration Bit Stream Generators
  • From: Pavel Korensky <pavelk@anet.cz>
• [oc] ATA-3 Core
  • From: jimkje@adaptivemicro.com
• Re: [oc] Re:
  • From: "Paul Baxter" <paul_baxter@ntlworld.com>
• [oc] bidirection pin on acex 1k30 from Altera
  • From: Daniel Haensse <daniel.haensse@alumni.ethz.ch>
• [oc] http://www.video2flash.com. Convert your videos into flash format!
  • From: video2flash@boldyonline.com
• Re: [oc] vhdl
  • From: Andras Ferencz <aferencz@usa.net>
• Re: [oc] Configuration Bit Stream Generators
  • From: Victor the Cleaner <jonathan@canuck.com>
• Re: [oc] vhdl
  • From: Daniel Haensse <daniel.haensse@alumni.ethz.ch>
• [oc] Re:
  • From: "Vladimir Rustinov" <rust@energo.waterpas.com>
• Re: [oc] vhdl
  • From: "Vladimir Rustinov" <rust@energo.waterpas.com>
• Re: [oc] vhdl
  • From: "Vladimir Rustinov" <rust@energo.waterpas.com>
• No Subject
  • From: amol morankar <morankaramol@yahoo.com>
• Re: [oc] new project...MP3 (audio) core?
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [oc] new project...MP3 (audio) core?
  • From: <asoel@ins.itb.ac.id>
• Re: [oc] 8051 core
  • From: Daniel Haensse <daniel.haensse@alumni.ethz.ch>
• [oc] Configuration Bit Stream Generators
  • From: "Dave Feustel" <dfeustel@mindspring.com>
• [oc] (no subject)
  • From: THEOWW20@aol.com
• RE: [oc] Newbie - How to get started?
  • From: "s g" <ssg@detroitlions.net>
• Re: [oc] new project...MP3 (audio) core?
  • From: John William Dalton <jdalton@asiaonline.net.au>
• No Subject
  • From: putu astawa <astawa80@yahoo.com>
• Re: [oc] Newbie - How to get started?
  • From: "hendra gunawan" <hendrag01@hotmail.com>
• [oc] Newbie - How to get started?
  • From: "s g" <ssg@detroitlions.net>
• RE: [oc] question regarding vhdl
  • From: "Olson, Gary" <GOlson@armillaire.com>
• [oc] upgrade of OC server
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [oc] new project...MP3 (audio) core?
  • From: "Marko Mlinar" <markom@opencores.org>
• [oc] question regarding vhdl
  • From: amol morankar <morankaramol@yahoo.com>
• Re: [oc] constraints while programming in VHDL
  • From: "Johnsonw10" <johnsonw10@hotmail.com>
• Re: [oc] new project...MP3 (audio) core?
  • From: "Damjan Lampret" <lampret@opencores.org>
• RE: [oc] new project...MP3 (audio) core?
  • From: "Dautel, Rob" <Dautel@AllAmerican.com>
• Re: [oc] 8051 core
  • From: Jamil Khatib <khatib@ieee.org>
• Re: [oc] 8051 core
  • From: John William Dalton <jdalton@asiaonline.net.au>
• Re: [oc] new project...MP3 (audio) core?
  • From: John William Dalton <jdalton@asiaonline.net.au>
• Re: [oc] new project...MP3 (audio) core?
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] constraints while programming in VHDL
  • From: Pavel Korensky <pavelk@anet.cz>
• Re: [oc] new project...MP3 (audio) core?
  • From: "Dirk Heise" <dheise@debitel.net>
• [oc] Re: new project...MP3 (audio) core?
  • From: Andreas Bombe <andreas.bombe@munich.netsurf.de>
• [oc] 8051 core
  • From: Daniel Haensse <daniel.haensse@alumni.ethz.ch>
• Re: [oc] new project...MP3 (audio) core?
  • From: lior.shtram@flextronicssemi.com
• Re: [oc] new project...MP3 (audio) core?
  • From: "Marko Mlinar" <markom@opencores.org>
• Re: [oc] new project...MP3 (audio) core?
  • From: volodya@mindspring.com
• Re: [oc] constraints while programming in VHDL
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] new project...MP3 (audio) core?
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] constraints while programming in VHDL
  • From: "hendra gunawan" <hendrag01@hotmail.com>
• [oc] new project...MP3 (audio) core?
  • From: "Dautel, Rob" <Dautel@AllAmerican.com>
• Re: [oc] Intersted in the new development
  • From: "Arshie" <arshie@hotmail.com>
• [oc] constraints while programming in VHDL
  • From: sandeep shastri <sandeep_shastri@yahoo.com>
• Re: [oc] Intersted in the new development
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] Intersted in the new development
  • From: "Arshie" <arshie@hotmail.com>
• [oc] Intersted in the new development
  • From: "Anand Gopal Shirahatti" <anandg_s@rediffmail.com>
• Re: [oc] Hello, I'm new.
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] Hello, I'm new.
  • From: "Damjan Lampret" <lampret@opencores.org>
• [oc] spam
  • From: "Damjan Lampret" <lampret@opencores.org>
• [oc] Hello, I'm new.
  • From: "Dautel, Rob" <Dautel@AllAmerican.com>
• [oc] System board design.
  • From: Alan Grimes <alangrimes@starpower.net>
• [oc] [META] List Spam
  • From: Alan Grimes <alangrimes@starpower.net>
• [oc] VGA/LCD Core
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] serial UART in cadence
  • From: nvenkat@ee.iitb.ac.in
• Re: [oc] Lookin for a MISC core
  • From: "Dirk Heise" <dheise@debitel.net>
• Re: [oc] VGA/LCD Core gate count estimate?
  • From: Richard Herveille <richard@asics.ws>
• [oc] VGA/LCD Core gate count estimate?
  • From: Bob Miller <bmiller@avg.net>
• [oc] INFO: How to download a core
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] DES Core
  • From: oma@263.net
• [oc] Article Link: Is DIY Dead?
  • From: jdalton@asiaonline.net.au
• [oc] Developing a Java Based Microcontroller in Verilog
  • From: Stephen P Schulz <schulzsp@nb.conexant.com>
• [oc] Education info
  • From: love2teach61@hotmail.com
• [oc] IPCore
  • From: "κÁú¸Õ" <vhdl_fpga@163.net>
• [oc] New web utility
  • From: Victor Black <content-management@high-tech-communcations.com>
• Re: [oc] Wishbone master multiple slave problem
  • From: daniel haensse <daniel.haensse@alumni.ethz.ch>
• Re: [oc] Lookin for a MISC core
  • From: Jecel Assumpcao Jr <jecel@merlintec.com>
• [oc] Lookin for a MISC core
  • From: "Dirk Heise" <dheise@debitel.net>
• Re: [oc] Wishbone master multiple slave problem
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] ATA core
  • From: Richard Herveille <richard@asics.ws>
• Objet :[oc] Wishbone master multiple slave problem (Out ofOffice Autoreply)
  • From: "Patrick Ditsch" <patrick.ditsch@tdf.fr>
• Re: [oc] ATA core
  • From: orenz@newmail.net
• Re: [oc] Interested
  • From: "Miha Dolenc" <mihad@opencores.org>
• [oc] Wishbone master multiple slave problem
  • From: daniel haensse <daniel.haensse@alumni.ethz.ch>
• Objet :Re: [oc] Interested (Out of Office Autoreply)
  • From: "Patrick Ditsch" <patrick.ditsch@tdf.fr>
• Objet :[oc] Interfacing a circuit with a video controller?(Outof Office Autoreply) (Out of Office Autoreply)
  • From: "Patrick Ditsch" <patrick.ditsch@tdf.fr>
• Objet :Re: [oc] Interfacing a circuit with a video controller?(Out of Office Autoreply)
  • From: "Patrick Ditsch" <patrick.ditsch@tdf.fr>
• Re: [oc] Interested
  • From: mjd001@yahoo.com
• Objet :[oc] Interfacing a circuit with a video controller?(Out of Office Autoreply)
  • From: "Patrick Ditsch" <patrick.ditsch@tdf.fr>
• Re: [oc] Interfacing a circuit with a video controller?
  • From: Richard Herveille <richard@asics.ws>
• [oc] Interfacing a circuit with a video controller?
  • From: Michael M Delaney <mmdst23+@pitt.edu>
• [oc] VGA/LCD Controller
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] dos attack
  • From: jdalton@asiaonline.net.au
• [oc] dos attack
  • From: Damjan Lampret <lampret@opencores.org>
• [oc] subscribe
  • From: Mike Randall <mike.randall@microprocessor-design.com>