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Re: [oc] question regarding vhdl



You don't need to worry about carry if you use one-bit wider result.
Ex: (It is NOT in VHDL as I do not remember the exact syntax).

To do SUM[7:0] <= A[7:0] +/- B[7:0]
Use
A_Expand[8:0] <= 0 & A[7:0];
B_Expand[8:0] <= 0 & B[7:0];
Addition A + B
SUM[8:0] <= A_Expand[8:0] + B_Expand[8:0]
2's complement subtraction: A - B
SUM[8:0] <= A_Expand[8:0] + (~B_Expand[8:0]) + 1

SUM[7:0] is the result and SUM[8] is the carry.

----- Original Message -----
From: "Olson, Gary" <GOlson@armillaire.com>
To: <cores@opencores.org>
Sent: Friday, July 20, 2001 9:39 AM
Subject: RE: [oc] question regarding vhdl


> Are you aware of the Concatenation operator in VHDL?  It is the & sign.
It
> allows two buses to be
> combined into one bus.  Or a single signal to be combined to a BUS.  See
the
> article
> at
> http://archives.e-insite.net/archives/ednmag/reg/1997/041097/08df_08.htm
>
>
> Concatenation and Verilog replication operators. In VHDL, the
concatenation
> operator "&" combines (concatenates) the bits of single- or multiple-bit
> operands on either side of the operator.
>
> Example might be
>
> ENTITY EXAMPLE ....  ( whatever )
>
> Architecture SYN of EXAMPLE IS
>
> signal CARRY : STD_LOGIC;
> signal B : STD_LOGIC_VECTOR(7 downto 0);
> signal RESULT : STD_LOGIC_VECTOR(8 downto 0);
> BEGIN
>
> RESULT <= CARRY & B;  <= this is a 9 bit result carry in the 9th position
>
> END ARCHITECTURE;
>
> Hope this helps with few syntax errors,
> Gary Olson
>
>
>
>
>
>
>
>
> -----Original Message-----
> From: amol morankar [mailto:morankaramol@yahoo.com]
> Sent: Thursday, July 19, 2001 11:21 PM
> To: cores@opencores.org
> Subject: [oc] question regarding vhdl
>
>
>  Hello Sir,
>                Myself Amol  , I am working on vhdl for
> my project. I have a problem regarding addition and
> substraction of bit vectors and concatentation of the
> result if carry is generated.
>            pls mail me the answer , Thank you.
>
>                                        amol
>
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