RE: [oc] bidirection pin on acex 1k30 from Altera

[Daniel Haensse <daniel.haensse@alumni.ethz.ch>]

yes, sorry about this, I send this email and then a have seen his email
sorry about this. I will put this work as an opencore (if anyone is interested).

Dani


Am Don, 26 Jul 2001 schrieben Sie:
> Dani,
> 
> I am a newcomer to the opencores arena.  I hope I'm not out of line here,
> but.. 
> 
> It appears the work being done here has great potential, and is being worked
> on my some very great minds.
> 
> I'd like to repeat the response give recently by Andy.
> 
> "I think we should stick to the goals of this mailing-list,
> whatever that means.
> 
> So, I believe that this sort of questions should be addressed
> to comp.lang.vhdl, comp.lang.verilog or another similar
> usenet group. Let us focus on the running projects or in finding
> new projects."
> 
> Let's not clutter up the boards with topics that should be addressed
> elsewhere.
> 
> -----Original Message-----
> From: Daniel Haensse [mailto:daniel.haensse@alumni.ethz.ch]
> Sent: Wednesday, July 25, 2001 9:40 AM
> To: cores@opencores.org
> Cc: cores@opencores.org
> Subject: [oc] bidirection pin on acex 1k30 from Altera
> 
> 
> Hi folks,
> 
> how can I implement a bidirectional port in vhdl. I try a inout declaration
> of
> the ioports. When the ports should be used as an input I use
> gpioport <= 'z';
> 
> using a ACEX 1k30 altera device I get an error that the compiler can't put
> the
> pin into tristate.
> Do I have to declare the same pin as input as well as output, just using
> names
> like
> in a process:
> ...
> iif gpiodirection='1' then
> 	gpioport_out <= 'z';
> else
> 	gpioport_out<=currentoutput;
> end if;
> currentinput <=gpioport_in;
> ...
> 
> Does anybody has a simple example
> 
> thank you 
> 
> Dani
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