Re: [oc] constraints while programming in VHDL

[Rudolf Usselmann <rudi@asics.ws>]

on 7/18/01 10:16, sandeep shastri at sandeep_shastri@yahoo.com wrote:

> Hello everybody, 
> Myself is Sandeep,and is a Post Graduate
> student and
> doing dissertation in JPEG baseline image compression
> using VLSI.
> I have written a code for 2-D DCT using VHDL and
> simulated it, but hte
> problem is that it is not fitting in any of the CPLD
> or FPGA. I have
> used Xilinx 2.1 tool.Is there any solution to this
> problem?????????/

It is very difficult to answer such general questions. You should
analyze your design and try to understand why it does not fit.
Perhaps it's just very big and you have to split it across several
FPGAs. It doesn't mean that there is something wrong with your
design or the tools.

However, to fill up one of the new million gates FPGAs takes a
really large design. I don't know enough about JPEG algorithms
to be able to judge. Here are a few tips that might help you.

1) Break up your design in to several small equally large modules
and try to synthesize and place each one of them independently.
If one of the blocks takes up a lot more space than the others
you know where to look.

2) Make sure you are not using standard HDL constructed memories.
Even though they will work, they will be huge. All memories should
be replaced with memories provided by the FPGA vendor. For
example use BlockRams with Xilinx FPGAs.

3) Same thing as for memories applies to arithmetic functions. It
is very easy to define two 64 bit vectors and perform a divide on
them. Doesn't look like a lot when writing HDL, but once synthesized
you'll be amazed how big a divider can get ! (This applies to all
math functions).

Similar as to the above examples, you should review your code
(or even better have someone else review your code - somebody
who can be very critical. Almost all companies that design custom
chips do that). Try to think about each line of code how it would
look drawn up as gates. I'll bet you if you do this you will
find the problem within a few hours !

> My doubt is that while writing the code is it
> necessary to take in to
> consideration the internal architecture of the FPGA or
> CPLD??? If yes
> then in which manner???????/

The only places where you really *should* take advantages of internal
structures are: Memories and Arithmetic functions.

Some FPGAs offer additional optimizations, but those are mostly
for timing. (I'm sure you'll be asking that question next ;*)

I can't say it enough: RTFM ! (Read The Freaking Manuals ;*)

> Thanking you in anticipation
> 
> Yours 
> sandeep

Cheers !
-- 
rudi


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