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[oc] Wishbone master multiple slave problem
Hi folks,
Can anybody explain to me, how one wishbone master must be interfaced to
multiple slaves. Is this done in the slave vhdl code or is a multiplexer of the
strobe signal used in the connection between master and slaves? I'm working on a
openhardware project at www.openhardware.net/Dragonix/index.php and we
have started to implement a simple master that will be mapped into the 68k
microprocessor memory space.
best
regards
Daniel Haensse
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