[oc] Contributing to an existing project

[Victor Snesarev <vnsnes@yahoo.com>]

Hello,

I have a couple of months off work (hopefully just a couple), and I 
would like to contribute to an existing project while I have free time.

I have 2 years of FPGA design/development/verification using Verilog, 
but have fundumental VHDL knowledge and several months of practice. I 
also have done several months of ASIC verification. I have access to 
free tools (Linux and Windows).

If you think I can help or have further questions, feel free to drop me 
a private e-mail.

Victor




_________________________________________________________
Do You Yahoo!?
Get your free @yahoo.com address at http://mail.yahoo.com

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml