Re: [oc] VGA/LCD Core gate count estimate?

[Richard Herveille <richard@asics.ws>]

At 09:56 AM 7/13/2001 -0500, you wrote:
>I am new to VHDL ( I don't know what I am doing yet, just learning), so this
>is something I should be able to figure out on my own once I understand
>this.
>
>Any idea how much of a Xilinx Spartin II FPGA 100K or 150K this (VGA/LCD Core)
>would use?

Spartan II Xc2s100-6-fg456, 793slices(66%) & 6 BlockRAMs(60%).

>  This core is quite interesting to me and I would like to propose changes to
>a product line based on putting the LCD controller inside the system FPGA.
>In addition I only need 8 bit color and up to 800 x 600 resolution.

The core supports 8bpp gray-scale, 8bpp pseudo color, 16bpp & 24bpp color 
modes. The additional modes use relatively few resources. If you do want to 
strip the core, you can do so by deleting the modes from the statemachine.

>This would reduce the gate count and the internal ram needed for buffers.

The core has still room for improvements. Gate count will reduce, when I 
get time to work on it.

>This would interface with a Motorola Coldfire processor.
>
>I am working on gaining a basic knowledge of VHDL thru Xilinx Foundation 
>software
>and compiling this core into the Spartin II family.  I am stumbling with a 
>couple problems,
>the embedded ram needs to be changed to take advantage on their specific 
>resources.

The rams are placed into Xilinx BlockRAMs and Altera EABs, what else do you 
want ?.

>The core also chokes on a for statement not supported error.

Let me know which one. The problem is the Xilinx Foundation software, it's 
VHDL compiler is far from finished.

Richard

>Any help would be appreciated!
>
>Bob
>bmiller@avg.net
>
>
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