[oc] constraints while programming in VHDL

["hendra gunawan" <hendrag01@hotmail.com>]

hi'

>Hello everybody,
>               Myself is Sandeep,and is a Post Graduate
>student and
>doing dissertation in JPEG baseline image compression
>using VLSI.
>I have written a code for 2-D DCT using VHDL and
>simulated it, but hte
>problem is that it is not fitting in any of the CPLD
>or FPGA. I have
>used Xilinx 2.1 tool.Is there any solution to this
>problem?????????/
you don't tell us what error message you've got. but maybe you assigned your 
input/output design to wrong I/O pin in FPGA, which can't be assigned as 
input/output

>My doubt is that while writing the code is it
>necessary to take in to
>consideration the internal architecture of the FPGA or
>CPLD??? If yes
>then in which manner???????/
i think you don't have to.

best regard

Hendra
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