[oc] constraints while programming in VHDL

[sandeep shastri <sandeep_shastri@yahoo.com>]

Hello everybody, 
              Myself is Sandeep,and is a Post Graduate
student and
doing dissertation in JPEG baseline image compression
using VLSI.
I have written a code for 2-D DCT using VHDL and
simulated it, but hte
problem is that it is not fitting in any of the CPLD
or FPGA. I have
used Xilinx 2.1 tool.Is there any solution to this
problem?????????/
My doubt is that while writing the code is it
necessary to take in to
consideration the internal architecture of the FPGA or
CPLD??? If yes
then in which manner???????/


Thanking you in anticipation


Yours 
sandeep

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