Re: [oc] constraints while programming in VHDL

[Pavel Korensky <pavelk@anet.cz>]

At 20:16 17.7.2001 -0700, you wrote:
>Hello everybody, 
>              Myself is Sandeep,and is a Post Graduate
>student and
>doing dissertation in JPEG baseline image compression
>using VLSI.
>I have written a code for 2-D DCT using VHDL and
>simulated it, but hte
>problem is that it is not fitting in any of the CPLD
>or FPGA. I have
>used Xilinx 2.1 tool.Is there any solution to this
>problem?????????/

It is strange, because there are some JPEG and M-JPEG codec implementations
as a commercially available cores which can fit into smaller Virtex FPGAs
and even in some Spartan2 FPGAs. 
If you are trying to synthetise your core in some Xilinx chips, maybe you
are using too much of special features like BlockRAM, BUFG buffers or PLLs...
Can you post the synthesis and place/route report ?

Best regards

PavelK


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