Re: [oc] constraints while programming in VHDL

["Johnsonw10" <johnsonw10@hotmail.com>]

I don't think the FPGA size is an issue because Xilinx has up to 10 million
gate FPGA's. My guess is that your VHDL code has some non-synthesizable
constructs. One of Xilinx manuals talks about the synthesizable contructs in
VHDL and Verilog. Take a look to see if it helps.

Jim
----- Original Message -----
From: "sandeep shastri" <sandeep_shastri@yahoo.com>
To: <cores@opencores.org>
Sent: Tuesday, July 17, 2001 11:16 PM
Subject: [oc] constraints while programming in VHDL


> Hello everybody,
>               Myself is Sandeep,and is a Post Graduate
> student and
> doing dissertation in JPEG baseline image compression
> using VLSI.
> I have written a code for 2-D DCT using VHDL and
> simulated it, but hte
> problem is that it is not fitting in any of the CPLD
> or FPGA. I have
> used Xilinx 2.1 tool.Is there any solution to this
> problem?????????/
> My doubt is that while writing the code is it
> necessary to take in to
> consideration the internal architecture of the FPGA or
> CPLD??? If yes
> then in which manner???????/
>
>
> Thanking you in anticipation
>
>
> Yours
> sandeep
>
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