Re: [oc] Wishbone master multiple slave problem

[Richard Herveille <richard@asics.ws>]

>Hi folks,
>
>Can anybody explain to me, how one wishbone master must be interfaced to
>multiple slaves. Is this done in the slave vhdl code or is a multiplexer 
>of the
>strobe signal used in the connection between master and slaves?

It's done by modifying the strobe signal (STB) in the connection between 
the master and the slaves. Use a decoder (address-decoder) instead of a 
multiplexor. AND (logical AND) the decoder outputs with the strobe signal.

Richard

>I'm working on a
>openhardware project at www.openhardware.net/Dragonix/index.php and we
>have started to implement a simple master that will be mapped into the 68k
>microprocessor memory space.
>
>best
>
>regards
>
>Daniel Haensse
>--
>To unsubscribe from cores mailing list please visit 
>http://www.opencores.org/mailinglists.shtml

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml