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• Re: [oc] core for FFT/IFFT (1024 point)for 802.11a protocol, z82302
• [oc] Ethernet crc32 VHDL anyone?, deepak_1980_r
  • Re: [oc] Ethernet crc32 VHDL anyone?, Colin Marquardt
  • Re: [oc] Ethernet crc32 VHDL anyone?, Amani
  • <Possible follow-up(s)>
  • RE: [oc] Ethernet crc32 VHDL anyone?, Ho, Wen Jei x4297
  • Re: [oc] Ethernet crc32 VHDL anyone?, kinysh asdf
• [oc] test_bench, leire.rubio
  • Re: [oc] test_bench, Colin Marquardt
  • Re: [oc] test_bench, John Sheahan
• [oc] Async reset: active high or active low?, Allan Herriman
  • <Possible follow-up(s)>
  • Re: [oc] Async reset: active high or active low?, cyrano
  • Re: [oc] Async reset: active high or active low?, Haytham Azmi
    • Re: [oc] Async reset: active high or active low?, Rudolf Usselmann
    • Re: [oc] Async reset: active high or active low?, Niclas Hedhman
  • Re: [oc] Async reset: active high or active low?, cyrano
    • Re: [oc] Async reset: active high or active low?, Rudolf Usselmann
  • Re: [oc] Async reset: active high or active low?, cyrano
    • Re: [oc] Async reset: active high or active low?, Rudolf Usselmann
    • Re: [oc] Async reset: active high or active low?, John Sheahan
      • Re: [oc] Async reset: active high or active low?, Niclas Hedhman
      • Re: [oc] Async reset: active high or active low?, Rudolf Usselmann
• RE: [oc] UART16550 core and 10/100 Base-T Core and GPIO Core, Ho, Wen Jei x4297
• RE: [oc] UART16550 core and 10/100 Base-T Core, Ho, Wen Jei x4297
  • <Possible follow-up(s)>
  • RE: [oc] UART16550 core and 10/100 Base-T Core, Ho, Wen Jei x4297
• [oc] Adder issues ?, NansonHuang
  • Re: [oc] Adder issues ?, Rudolf Usselmann
  • Re: [oc] Adder issues ?, Joachim Strömbergson
    • Re: [oc] Adder issues ?, Rudolf Usselmann
  • Re: [oc] Adder issues ?, John Sheahan
• [oc] Trade off between area and power ?, NansonHuang
  • Re: [oc] Trade off between area and power ?, Rudolf Usselmann
    • Re: [oc] Trade off between area and power ?, John Sheahan
• Re: [oc] 8255 PPI source code, veena_3_2003
  • Re: [oc] 8255 PPI source code, MikeJ
• [oc] =?gb2312?B?tPC4tDogW29jXSBWSERMIFByb2Nlc3Mgc3RhdGVtZW50?=, lin.sheng
• [oc] VHDL Process statement, twebel
  • RE: [oc] VHDL Process statement, Radwin Zagala
• Re: [oc] Suggesting H263 codec core, ha_delbari
• [oc] Hi, may we be friends?, liu yuxue
  • Re: [oc] Hi, may we be friends?, Chenbo Liu
• [oc] video_compression_systems document, kinysh asdf
  • Re: [oc] video_compression_systems document, Richard Herveille
  • <Possible follow-up(s)>
  • RE: [oc] video_compression_systems document, Naveena Padmaraju
• Re: [oc] NEWS-FLASH: Free VHDL to Verilog Translator, yanzhang1999
  • <Possible follow-up(s)>
  • RE: [oc] NEWS-FLASH: Free VHDL to Verilog Translator, liu, zhigang
• [oc] PS/2 mouse & keyboard Wishbone core, Daniel Quintero
  • Re: [oc] PS/2 mouse & keyboard Wishbone core, Marko Mlinar
  • RE: [oc] PS/2 mouse & keyboard Wishbone core, Igor Mohor\(opencores\)
    • RE: [oc] PS/2 mouse & keyboard Wishbone core, Rudolf Usselmann
• [oc] How to model capacitor in Verilog??, kokloon
  • <Possible follow-up(s)>
  • RE: [oc] How to model capacitor in Verilog??, sphuynh
  • RE: [oc] How to model capacitor in Verilog??, kinysh asdf
  • RE: [oc] How to model capacitor in Verilog??, sphuynh
• [oc] Xilinx -> ALdec Core compatibility, kartik
• Re: [oc] Re: code for usart, roopa_ranganath
• [oc] UART16550, tate
  • Re: [oc] UART16550, John Sheahan
  • Message not available
    • Re: [oc] UART16550, Steve Tate
  • <Possible follow-up(s)>
  • RE: [oc] UART16550, Harvey, Wilbur
  • FW: [oc] UART16550, Ho, Wen Jei x4297
• [oc] WTB & MVB protocols, vdesign
  • Re: [oc] WTB & MVB protocols, Joachim Strömbergson
    • Re: [oc] WTB & MVB protocols, Armando Astarloa
• [oc] Inquiry, Rudolf Usselmann
• [oc] IEEE802.11 MAC core, youlong
• [oc] DCT Project [ROM64 and others], Héctor Orón Martínez
  • Re: [oc] DCT Project [ROM64 and others], Richard Herveille
• [oc] Can I get the time integrating correlator's verilog source code?, uzunlarovunc
• [oc] How Do I Make UART EDIFs in Macros for Use in Projects?, Benson Wong
  • Re: [oc] How Do I Make UART EDIFs in Macros for Use in Projects?, Michael Ayton
  • Re: [oc] How Do I Make UART EDIFs in Macros for Use in Projects?, Armando Astarloa
• Re: [oc] Open Core Forth Processor, dyy1511
• [oc] projects, albert raj a
  • Re: [oc] projects, Holger Baxmann
  • Re: [oc] projects, Shehryar Shaheen
• [oc] ARM Core, porschen
  • Re: [oc] ARM Core, Rudolf Usselmann
  • <Possible follow-up(s)>
  • Re: [oc] ARM Core, ritesh
  • Re: [oc] ARM Core, nissimd
  • Re: Re: [oc] ARM Core, ritesh
  • Re: Re: [oc] ARM Core, ritesh
• [oc] async/sync reset., nico
  • Re: [oc] async/sync reset., Rudolf Usselmann
  • <Possible follow-up(s)>
  • Re: [oc] async/sync reset., cyrano
    • Re: [oc] async/sync reset., Rudolf Usselmann
    • Re: [oc] async/sync reset., Joachim Strömbergson
    • Re: [oc] async/sync reset., John Sheahan
  • Re: [oc] async/sync reset., cyrano
  • Re: [oc] async/sync reset., cyrano
    • Re: [oc] async/sync reset., Rudolf Usselmann
    • Re: [oc] async/sync reset., manxi wang
  • Re: [oc] async/sync reset., kinysh asdf
• Re: Re: [oc] PLL vs DLL, kinysh asdf
• [oc] Re: Fwd: [Fwd: Fwd: Fw: I love India], ritesh
• [oc] [Fwd: Industry Gadfly "VHDL, the new Latin"], Rudolf Usselmann
  • Re: [oc] [Fwd: Industry Gadfly "VHDL, the new Latin"], Holger Baxmann
• [oc] or1200's or1200_ctrl.v, qcpassed
  • Re: [oc] or1200's or1200_ctrl.v, Marko Mlinar
• [oc] Xscale, etc. and IP, shr
  • Re: [oc] Xscale, etc. and IP, Joachim Strömbergson
  • <Possible follow-up(s)>
  • Re: [oc] Xscale, etc. and IP, kinysh asdf
    • Re: [oc] Xscale, etc. and IP, Joachim Strömbergson
      • Re: [oc] Xscale, etc. and IP, Jayaprakash Balachandran
      • Re: [oc] Xscale, etc. and IP, Holger Baxmann
• [oc] need help about or1200's freeze logic, qcpassed
• [oc] z80 code, Ian MacPherson
• Re: [oc] VHDL Simulation Model for 24C02, ysli
  • Re: [oc] VHDL Simulation Model for 24C02, Richard Herveille
• [oc] help about or1k's dmmu, qcpassed
  • <Possible follow-up(s)>
  • Re: [oc] help about or1k's dmmu, qcpassed
• Re: [oc] Final Year University Projects, Alexander Groisman
• [oc] verilog to vhdl converter, John Sheahan
  • Re: [oc] verilog to vhdl converter, Rudolf Usselmann
    • Re: [oc] verilog to vhdl converter, John Dalton
      • Re: [oc] verilog to vhdl converter, Rudolf Usselmann
      • Re: [oc] verilog to vhdl converter, Damjan Lampret
      • Re: [oc] verilog to vhdl converter, Rudolf Usselmann
      • Re: [oc] verilog to vhdl converter, Graham Seaman
    • Re: [oc] verilog to vhdl converter, Damjan Lampret
      • Re: [oc] verilog to vhdl converter, Rudolf Usselmann
    • Re: [oc] verilog to vhdl converter, John Sheahan
  • Re: [oc] verilog to vhdl converter, Niclas Hedhman
    • Re: [oc] verilog to vhdl converter, John Sheahan
  • <Possible follow-up(s)>
  • Re: [oc] verilog to vhdl converter, leire.rubio
• Re: [oc] UART16550 core, Matthias Fuchs
  • <Possible follow-up(s)>
  • Re: [oc] UART16550 core, khchang
  • RE: [oc] UART16550 core, Ho, Wen Jei x4297
    • RE: [oc] UART16550 core, Igor Mohor\(opencores\)
• [oc] Twofish implementation question, spyros
  • <Possible follow-up(s)>
  • Re: [oc] Twofish implementation question, henry_xb
• [oc] RE: [pci] PCI core ( LICENSING ), Tadej Markovic
  • Re: [oc] RE: [pci] PCI core ( LICENSING ), Rudolf Usselmann
  • Re: [oc] RE: [pci] PCI core ( LICENSING ), Richard Herveille
    • Re: [oc] RE: [pci] PCI core ( LICENSING ), Johan Klockars
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Richard Herveille
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Johan Klockars
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Rudolf Usselmann
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Joachim Strömbergson
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Richard Herveille
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Kevin Kilzer
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Rudolf Usselmann
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), nico
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), nico
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Cyrano
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Niclas Hedhman
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), John Dalton
      • Re: [oc] RE: [pci] PCI core ( LICENSING ), Graham Seaman
  • <Possible follow-up(s)>
  • Re: [oc] RE: [pci] PCI core ( LICENSING ), cyrano
• [oc] Serila DAA in verilog, Tanveer Shariff
• [oc] Synthzable rom, Tanveer Shariff
• [oc] task usage in verilog, lin.sheng
• [oc] design methodology, leire.rubio
  • Re: [oc] design methodology, Richard Herveille
  • Re: [oc] design methodology, Rudolf Usselmann