RE: [oc] NEWS-FLASH: Free VHDL to Verilog Translator

["liu, zhigang" <liu_zhigang@emc.com>]

Zhang Yan:

How are you? This is Alpha!
If you unzip the files using windows stuff such as winzip, you will have
trouble to build. 



-----Original Message-----
From: yanzhang1999@hotmail.com [mailto:yanzhang1999@hotmail.com]
Sent: Monday, April 21, 2003 3:39 AM
To: cores@opencores.org
Subject: Re: [oc] NEWS-FLASH: Free VHDL to Verilog Translator


Hi, All,
 
I could not successfully compile the vhd2vl program for windows. I got 
source file from following link,
 
http://www.ocean-logic..com/pub/vhd2vl.tgz
 
I build cygwin and gcc, bison and flex in my w2k, but the gcc found a 
lot of format error.
 
Would someone help me?
 
Besides, could any one tell me how to make executable in cygwin. The 
make install file have to  use some "make".
 
Thanks!
 
Yan
----- Original Message ----- 
From: Rudolf Usselmann <rudi@a... > 
To: OpenCores Mailing List <cores@o... > 
Date: Sat, 21 Sep 2002 20:09:47 +0700 
Subject: [oc] NEWS-FLASH: Free VHDL to Verilog Translator 

> 
> 
> 
> I don't know if you guys have seen this but there is a free 
> VHDL to Verilog translation tool that was mentioned in a 
> recent EEtimes article. 
> 
> This is the EEtimes article: 
> http://www.eetasia.com/ART_8800272174_499481,499482.HTM 
> 
> This is the company offering it (download page): 
> at www.ocean-logic.com/downloads.htm 
> 
> Regards, 
> rudi 
> 
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