Re: [oc] async/sync reset.

[<cyrano@nerim.net>]

Rudolf Usselmann <rudi@asics.ws> a écrit :

> On Thu, 2003-04-10 at 07:20, nico wrote:
> > In most design guides, reset must be asynchronous to avoid hasard at
> 
> Oh really ?!  What hazard would that be ?
> 

Mostly, the behavior of the output of the chip, during the power up and the beginning of the clock.

> > power up. But in manual of Synopsys Design Compiler, they incourage the
> > use of synchronous reset.
> 
> Async resets are very dangerous and very difficult

:) Funny. It's seems that it is another religious war. In the lab where i work, sync reset are forbiden.

> to get right (specially if all you do is believing
> some "guidelines" how to do things right).
> 
> Avoid using async resets unless you absolutely have
> too AND fully understand the implication of it and
> how to do it right.
> 
> Assertion of Async reset is not a problem it's the
> de-assertion of it that has to be done right. Even
> if you do it right many design tools have problems
> with async reset. Static timing analysis (part of
> Synopsys Design Compiler) is on of those tools.
> 

So like an async set of the reset but  sync unset of the reset ?

> 
> > So, what do you use and why ?
> > 
> > nicO
> 
> Here is a link to an excellent white paper discussing
> all the pros and cons of Sync/Async reset.
> 
> http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets_rev1_1.pdf
> 

i will read it thanks.

nicO

> Regards, 
> rudi
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