[oc] task usage in verilog

[lin.sheng@zte.com.cn]

Hi,All,
  I have some dout about the usage of task when used to create my
testbench.
It seems that the task can only affect the signal when it returns, that is
to say, the signal can not change in the task.
following is the source code changed from the example from the verilog
standard. Simulation results that red, amber, green
always keep off. Any body are welcome to give suggestion. By the way, the
simulation tool I use is modelsim 5.5d.

Thanks.



module tranfic_lights;
reg clock, red, amber, green;
parameter on = 1, off = 0, red_tics = 15,
          amber_tics = 10, green_tics = 20;

initial red = off;
initial amber = off;
initial green = off;

always
  begin
  light(red, red_tics);
  light(green, green_tics);
  light(amber,amber_tics);
  $stop;
  end

task light;
  output color;
  input[31:0] tics;
begin
  color = on;
  repeat(tics) @(posedge clock);
  color = off;
end
endtask

always
  begin
  #10 clock = 0;
  #10 clock = 1;
  end

endmodule


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