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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v
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[cvs-checkins] mips/ ools/makefile ools/test.c hdl/alu.vhd hd ...
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[cvs-checkins] gpio/ ench/verilog/tb_tasks.v tl/verilog/gpio_ ...
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[cvs-checkins] mips/ ools/test.c hdl/bus_mux.vhd hdl/code.txt ...
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[cvs-checkins] mips/tools test.c
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[cvs-checkins] mips/vhdl tbench.vhd.txt
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[cvs-checkins] or1k/or1ksim/cpu/or32 execute.c
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[cvs-checkins] or1k/or1ksim/cpu/or32 or32.c
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[cvs-checkins] or1k/gen_or1k_isa Makefile sources/gen_or1k_isa.c
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[cvs-checkins] or1k/or1ksim sim-config.c
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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v uart_receive ...
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[cvs-checkins] or1k/gcc/gcc/config/or32 or32.S
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[cvs-checkins] dbg_interface/rtl/verilog dbg_top.v
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[cvs-checkins] or1k/gen_or1k_isa Makefile
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[cvs-checkins] or1k/gen_or1k_isa/sources or1k_isadesc.h
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[cvs-checkins] or1k/or1ksim sim.cfg
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[cvs-checkins] vapi/. gpio.c
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[cvs-checkins] or1k/or1ksim/cpu/or32 execute.c
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[cvs-checkins] or1k/or1ksim sim-config.c
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[cvs-checkins] or1k/or1ksim/testbench mmu.c
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[cvs-checkins] or1k/or1ksim gdb.h sim-config.c sim-config.h s ...
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[cvs-checkins] or1k/or1ksim/testbench mc_common.c
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[cvs-checkins] or1k/binutils opcodes/or32.c include/opcode/or32.h
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[cvs-checkins] or1k/gen_or1k_isa README
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[cvs-checkins] or1k/gen_or1k_isa/sources or32.c
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[cvs-checkins] or1k/gen_or1k_isa/sources/opcode or32.h
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[cvs-checkins] or1k/gcc/gcc/config/or32 or32.c
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[cvs-checkins] or1k/binutils/gas/config tc-or32.c
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[cvs-checkins] or1k/or1ksim/testbench mc_async.h
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[cvs-checkins] or1k/or1ksim/testbench mc_async.c
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[cvs-checkins] or1k/or1ksim/testbench mc_sync.c
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[cvs-checkins] or1k/or1ksim/testbench mc_sync.h
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[cvs-checkins] uart16550/rtl/verilog uart_debug_if.v uart_top.v
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[cvs-checkins] or1k/or1ksim/testbench mc_ssram.h
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[cvs-checkins] or1k/or1ksim/testbench mc_ssram.c
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[cvs-checkins] or1k/or1ksim/testbench mc_common.c
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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v uart_reg ...
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v uart_receiver.v
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[cvs-checkins] or1k/or1ksim/testbench mmu.c
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[cvs-checkins] or1k/or1ksim/testbench except_main.c except_test.S
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[cvs-checkins] or1k/or1ksim/cpu/or1k sprs.c
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[cvs-checkins] or1k/or1ksim/cpu/or1k except.c
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[cvs-checkins] or1k/or1ksim toplevel.c
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[cvs-checkins] or1k/or1ksim/cpu/or32 execute.c
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[cvs-checkins] uart16550/rtl/verilog uart_fifo.v
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[cvs-checkins] cordic/documentation cordic.pdf cordic.doc
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[cvs-checkins] or1k/or1ksim/testbench except.S
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[cvs-checkins] or1k/or1ksim/testbench Makefile.am Makefile.in
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[cvs-checkins] or1k/or1ksim/testbench excpt.S
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[cvs-checkins] or1k/or1ksim/cpu or32/execute.c or1k/except.c ...
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[cvs-checkins] uart16550/rtl/verilog uart_transmitter.v uart_ ...
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v
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[cvs-checkins] or1k/or1ksim/testbench mmu.c mmu.cfg
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[cvs-checkins] or1k/or1ksim/mmu immu.c dmmu.c
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[cvs-checkins] sxp/int_cont/src int_cont.v
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[cvs-checkins] sxp/src sxp.v
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[cvs-checkins] sxp/regf/src regf_status.v
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[cvs-checkins] sxp/src sxp.v
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[cvs-checkins] or1k/or1ksim/testbench except_mc.ld
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[cvs-checkins] or1k/or1ksim/testbench except_mc.S
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[cvs-checkins] or1k/or1ksim/testbench Makefile.am
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v
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[cvs-checkins] or1k/or1ksim/cpu/or1k except.c sprs.c
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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v
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[cvs-checkins] or1k/or1ksim/testbench mmu.cfg
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[cvs-checkins] or1k/or1ksim/testbench mmu.c
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[cvs-checkins] or1k/or1ksim/peripheral gpio.c
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[cvs-checkins] uart16550/rtl/verilog uart_debug_if.v
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[cvs-checkins] gpio/rtl/verilog gpio_top.v
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[cvs-checkins] vapi/. uart
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[cvs-checkins] or1k/or1ksim/testbench except.ld
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[cvs-checkins] or1k/or1ksim/vapi vapi.c
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[cvs-checkins] or1k/or1ksim/testbench except.S
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[cvs-checkins] or1k/or1ksim/vapi vapi.c vapi.h
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[cvs-checkins] or1k/or1ksim sim-config.c sim-config.h debug/g ...
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[cvs-checkins] or1k/or1ksim/mmu dmmu.c
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[cvs-checkins] or1k/or1ksim/cpu common/abstract.c or32/execut ...
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[cvs-checkins] or1k/jtag Makefile gdb.h jp1.c
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v
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[cvs-checkins] or1k/or1ksim sim-config.c sim.cfg
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[cvs-checkins] or1k/or1ksim/testbench basic.S
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[cvs-checkins] or1k/or1ksim/cpu/or32 execute.c
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[cvs-checkins] gpio/rtl/verilog gpio_top.v
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[cvs-checkins] mem_ctrl/rtl/verilog mc_defines.v
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[cvs-checkins] sxp/src sxp.v
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[cvs-checkins] or1k/or1ksim cpu/common/abstract.c mmu/dmmu.c ...
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[cvs-checkins] or1k/or1ksim sim-config.c sim-config.h sim.cfg ...
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[cvs-checkins] uart16550/rtl/verilog uart_defines.v
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[cvs-checkins] mem_ctrl/rtl/verilog mc_cs_rf.v mc_defines.v m ...
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[cvs-checkins] uart16550/rtl/verilog uart_regs.v
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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v
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[cvs-checkins] vapi/. uart uart.c
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[cvs-checkins] or1k/or1ksim peripheral/16450.c peripheral/164 ...
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[cvs-checkins] or1k/or1ksim/testbench functest.c
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[cvs-checkins] or1k/or1ksim/testbench excpt.S
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[cvs-checkins] or1k/or1ksim sim-config.c sim-config.h testben ...
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[cvs-checkins] or1k/or1ksim/testbench mmu.c
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[cvs-checkins] ethernet/bench/verilog tb_eth_top.v
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[cvs-checkins] or1k/or1ksim/testbench mmu.c mmu_asm.S
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[cvs-checkins] or1k/or1ksim/testbench Makefile.in basic.s cfg ...
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[cvs-checkins] or1k/or1ksim/testbench mmu.c
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[cvs-checkins] Import
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[cvs-checkins] or1k/or1ksim peripheral/16450.c peripheral/164 ...
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[cvs-checkins] or1k/or1ksim/testbench Makefile.am Makefile.in ...
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[cvs-checkins] sxp/src sxp.v
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[cvs-checkins] uart16550/ tl/verilog/uart_receiver.v tl/veril ...
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[cvs-checkins] dbg_interface/rtl/verilog dbg_defines.v
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[cvs-checkins] dbg_interface/rtl/verilog dbg_crc8_d1.v
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[cvs-checkins] or1k/or1ksim peripheral/16450.c peripheral/164 ...
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[cvs-checkins] sxp/src sxp.v
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[cvs-checkins] ethernet/doc eth_speci.pdf
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[cvs-checkins] ethernet/doc/src eth_speci.doc
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[cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_registe ...
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[cvs-checkins] or1k/or1ksim/peripheral ethernet.c
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[cvs-checkins] dbg_interface/rtl/verilog dbg_top.v
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[cvs-checkins] or1k/jtag Tag: mp3_stable Makefile gdb.h jp1.c
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[cvs-checkins] or1k/jtag
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[cvs-checkins] ethernet/rtl/verilog eth_top.v eth_wishbonedma.v
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[cvs-checkins] ethernet/rtl/verilog eth_registers.v
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[cvs-checkins] ethernet/rtl/verilog eth_defines.v
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] ethernet/doc/src eth_speci.doc
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] ethernet/doc eth_speci.pdf
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] sxp/src sxp.v
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[cvs-checkins] sxp/sim i_runtest
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[cvs-checkins] sxp/dpmem/src dpmem.v
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[cvs-checkins] sxp/int_cont/src int_cont.v
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[cvs-checkins] uart16550/rtl/verilog uart_debug_if.v
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[cvs-checkins] dbg_interface/doc/src DbgSupp.doc
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] dbg_interface/doc DbgSupp.pdf
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[cvs-checkins] or1k/gdb-5.0/gdb remote-or1k.c
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[cvs-checkins] or1k/gdb-5.0/gdb or1k-tdep.c
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[cvs-checkins] or1k/gdb-5.0/gdb/config/or1k tm-or1k.h
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[cvs-checkins] or1k/mp3/rtl/verilog/or1200 multp2_32x32.v gen ...
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[cvs-checkins] uart16550/ ench/verilog/uart_test.v oc/UART_sp ...
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] ethernet/doc eth_speci.pdf
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] ethernet/doc/src eth_speci.doc
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[cvs-checkins] ethernet/联系方法 邮件.txt
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[cvs-checkins] ethernet/联系方法
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] sxp/sim test_sxp.v
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: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
[cvs-checkins] sxp/sim test.sxp
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[cvs-checkins] sxp/regf/src regf_status.v
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[cvs-checkins] firewire/doc fw_link_working.pdf
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