[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] uart16550/rtl/verilog uart_debug_if.v

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/12/04 22:14:20

Added files:
	rtl/verilog    : uart_debug_if.v 

Log message:
	committed the debug interface file

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml