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[cvs-checkins] or1k/or1ksim/testbench mmu.c

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] or1k/or1ksim/testbench mmu.c
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Wed, 19 Dec 2001 15:44:34 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	simons	01/12/19 15:44:34

Modified files:
	or1ksim/testbench: mmu.c 

Log message:
	RTL_SIM define added for shorter simulation runtime.

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