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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] uart16550/rtl/verilog uart_receiver.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Mon, 10 Dec 2001 20:52:09 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/12/10 20:52:09

Modified files:
	rtl/verilog    : uart_receiver.v 

Log message:
	Igor fixed break condition bugs

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