Mail Index

• Thread Index

• Re: [oc] UART16550 core
  • From: ddresdner@pinnaclesys.com
• [oc] help needed in LCD basics
  • From: vikas_lcd@indiatimes.com
• Re: [oc] urgent
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• Re: [oc] urgent
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• Re: [oc] Operating system for 6811
  • From: Jerry Hicks <gehixz@bellsouth.net>
• Re: [oc] urgent
  • From: "Sudarshan" <sudarshan@ionicmicro.com>
• RE: [oc] Operating system for 6811
  • From: "John Moran" <jtmoran@mail.wsu.edu>
• [oc] urgent
  • From: AmitShah124@hotmail.com
• [oc] (ad)Strong WebRobot/eMailId Collector: Free Download !
  • From: <herald@ns1.nabitel.com>
• Re: [oc] Operating system for 6811
  • From: "Juan José 'Peco' San Martín" <peco@microbotica.es>
• [oc] Operating system for 6811
  • From: "John Moran" <jtmoran@mail.wsu.edu>
• Re: [oc] ARM Processor Verilog Model Request !
  • From: arunabhdas@yahoo.com
• Re: [oc] VHDL Simulation Model for 24C02
  • From: Richard Herveille <richard@asics.ws>
• [oc] VHDL Simulation Model for 24C02
  • From: "Robert Taubner" <robert.taubner@sigmatek.at>
• [oc] HDLC Core fit to Xilinx
  • From: chris.cornish@xilinx.nospam.com
• Re: [oc] IEEE802.11 MAC core
  • From: mohamed.kilani_ecc@m4x.org
• [oc] A Story of Rafaele CIRIELLO;
  • From: maria_schroder@hotmail.com
• [oc] Hi, long time !
  • From: <girlygirl0142r80@aol.com>
• [oc] NEWS-FLASH: Free VHDL to Verilog Translator
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Digital filters in for ASICs
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] FPGA based I2C interface
  • From: Richard Herveille <richard@asics.ws>
• [oc] FPGA based I2C interface
  • From: shivraj_v@rediffmail.com
• Re: [oc] help
  • From: "Sudarshan" <sudarshan@ionicmicro.com>
• Re: [oc] help
  • From: "Sushanta J. Sarmah" <sushanta@hyd.hellosoft.com>
• [oc] help
  • From: "Sudarshan" <sudarshan@ionicmicro.com>
• Re: [oc] IEEE802.11 MAC core
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] IEEE802.11 MAC core
  • From: "Sudarshan" <sudarshan@ionicmicro.com>
• Re: [oc] Digital filters in for ASICs
  • From: "Sudarshan" <sudarshan@ionicmicro.com>
• Re: [oc] IEEE802.11 MAC core
  • From: "alex" <alexanda@sjtu.edu.cn>
• Re: [oc] pseudo random generator verilog code source
  • From: Victor Snesarev <vnsnes@yahoo.com>
• Re: [oc] pseudo random generator verilog code source
  • From: olupas@opencores.org
• Re: [oc] pseudo random generator verilog code source
  • From: Bjorn Olsson <Bjorn.Olsson@InformAsic.com>
• [oc] Digital filters in for ASICs
  • From: paulb@pyronix.com
• [oc] IEEE802.11 MAC core
  • From: "Sudarshan" <sudarshan@ionicmicro.com>
• [oc] NEW ! USB 1.1 Function IP Core
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] pseudo random generator verilog code source
  • From: Marko Mlinar <markom@opencores.org>
• [oc] pseudo random generator verilog code source
  • From: "Dharmeshbhai PATEL" <dpatel@ifrance.com>
• Re: [oc] vhdl to verilog converter
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• [oc] =?gb2312?B?tPC4tDogW29jXSBJQyBkZXNpZ24=?=
  • From: "Zhichong Chen (Beijing)" <ZhichongChen@viatech.com.cn>
• [oc] IC design
  • From: "zhouhua" <rebackhua@hotmail.com>
• Re: [oc] FW: [openip] Brave GNU World (fwd)
  • From: "OpenCores FAQ Maintainer (John Dalton)" <faq@opencores.org>
• Re: [oc] vhdl to verilog converter
  • From: "sriramanan krishnamurthy" <sapota@hotmail.com>
• RE: [oc] vhdl to verilog converter
  • From: sphuynh <sphuynh@micron.com>
• [oc] vhdl to verilog converter
  • From: phamquang@hotmail.com
• [oc] FW: [openip] Brave GNU World (fwd)
  • From: "Jamil Khatib" <jamilkhatib@haridy.com>
• [oc] NEW ! Single Slot PCM Interface
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] NEW ! Simple Asynchronous Serial Controller
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] Re: MP3 Encoder?
  • From: Anent Prakash <anentscm@yahoo.com>
• [oc] NEW! USB 1.1 Phy Released
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] IC design
  • From: "zhouhua" <rebackhua@hotmail.com>
• Re: [oc] IC design
  • From: "Edward Wang" <ewang@ArcadiaDesign.com>
• [oc] IC design
  • From: "zhouhua" <rebackhua@hotmail.com>
• Re: [oc] HLLs vs HDLs
  • From: Colin Marquardt <c.marquardt@alcatel.de>
• Re: [oc] HLLs vs HDLs
  • From: Billditt@aol.com
• Re: [oc] HLLs vs HDLs
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] HLLs vs HDLs
  • From: Shehryar Shaheen <shehryar.shaheen@ul.ie>
• Re: [oc] i2c core with DS1621 (temp sensor)
  • From: sqshi@sdu.edu.cn
• Re: [oc] MP3 Encoder?
  • From: John Dalton <john.dalton@bigfoot.com>
• Re: [oc] MP3 Encoder?
  • From: shriketan@ieee.org
• [oc] Intel's push for DRM and the OCRP
  • From: John Dalton <john.dalton@bigfoot.com>
• [oc] Re:
  • From: praxismd@pcnet.ro
• [oc] Re:
  • From: praxismd@pcnet.ro
• Re: [oc] Open architecture of FPGA
  • From: "Tony Burch" <tony@burched.com.au>
• Re: Re[2]: [oc] Open architecture of FPGA
  • From: Marko Mlinar <markom@opencores.org>
• Re[2]: [oc] Open architecture of FPGA
  • From: "Alexander A. Shabarshin" <shaos@mail.ru>
• Re: [oc] can you give vhl code for 8253
  • From: soumitrasarkar@rediffmail.com
• Re: [oc] Open architecture of FPGA
  • From: Marko Mlinar <markom@opencores.org>
• [oc]
  • From: "zhouhua" <rebackhua@hotmail.com>
• [oc] Open architecture of FPGA
  • From: "Alexander A. Shabarshin" <shaos@mail.ru>
• [oc]
  • From: "zhouhua" <rebackhua@hotmail.com>
• [oc] WISHBONE Rev.B3 released.
  • From: Richard Herveille <richard@asics.ws>
• [oc] OFDM-looking for something more
  • From: "Jerzy G" <furia1024@wp.pl>
• Re: Re: [oc] DPLL or similar
  • From: Xianyang Jiang <xy_jiang@netease.com>
• Re: [oc] DPLL or similar
  • From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
• Re: Re: [oc] DPLL or similar
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: Re: [oc] DPLL or similar
  • From: Xianyang Jiang <xy_jiang@netease.com>
• Re: [oc] DPLL or similar
  • From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
• Re: [oc] DPLL or similar
  • From: bruce@bytes.co.za
• Re: [oc] ncverilog error message/ signal scan
  • From: "Miha Dolenc" <mihad@opencores.org>
• [oc] ncverilog error message/ signal scan
  • From: jae lim <jlim0011@yahoo.com>
• Re: [oc] Syntax errors in OCIDEC -Details
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] Is OCIDEC (and other opencore-cores) ill-suited for FPGA's?
  • From: Richard Herveille <richard@asics.ws>
• Re: [oc] Syntax errors in OCIDEC -Details
  • From: Shehryar Shaheen <shehryar.shaheen@ul.ie>
• [oc] Syntax errors in OCIDEC -Details
  • From: Volker Urban <volker.urban@web.de>
• Re: [oc] Is OCIDEC (and other opencore-cores) ill-suited for FPGA's?
  • From: Marko Mlinar <markom@opencores.org>
• Re: [oc] MP3 ENCODE AND DECODE SPEC
  • From: Marko Mlinar <markom@opencores.org>
• Re: [oc] Is OCIDEC (and other opencore-cores) ill-suited for FPGA's?
  • From: Volker Urban <volker.urban@web.de>
• Re: [oc] Is OCIDEC (and other opencore-cores) ill-suited for FPGA's?
  • From: Richard Herveille <richard@asics.ws>