[oc] HDLC Core fit to Xilinx

[chris.cornish@xilinx.nospam.com]

Hi,

I've tried fitting the single channel HDLC core to a Xilinx Virtex-II family 
device and have the following metrics:
Size is 263 slices
GCLK buffer usage is 3
Speed is 97MHz 
(This is for CLK_I, 215MHz for RxClk and 291MHz for TxClk, for what this 
is worth)

This is using Synplify PRO synthesis, 4.2.03i Xilinx software and a clock 
constraint of 61ns and targeting a xc2v80-fg256-4 device with default 
tool settings and efforts.

The design was taken as is and uses no block memory or other 
architectural features.

Details are:
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                  263 out of     512   51%
   Number of Slices containing
      unrelated logic:                 90 out of     263   34%
   Number of Slice Flip Flops:        339 out of   1,024   33%
   Total Number 4 input LUTs:         504 out of   1,024   49%
      Number used as LUTs:                          373
      Number used as a route-thru:                    3
      Number used for 32x1 RAMs:                    128
      (Two LUTs used per 32x1 RAM)
   Number of bonded IOBs:              82 out of     120   68%
      IOB Flip Flops:                                39
   Number of GCLKs:                     3 out of      16   18%
Total equivalent gate count for design:  22,126
Additional JTAG gate count for IOBs:  3,936

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