Re: [oc] DPLL or similar

[Allan Herriman <allan_herriman.hates.spam@agilent.com>]

Hi Bruce,

You might like to try:

http://fractional_divider.tripod.com/

Regards,
Allan.

bruce@bytes.co.za wrote:
> 
> Could you please email me a copy of this software or send some
> information on a fractional N divider which I need to implement on an
> FPGA, to generate the various bit ratea required for an MP3 decoder
> 
> Regards,
> Bruce
> 
> ----- Original Message -----
> From: Allan Herriman <allan_herriman.hates.spam@a... >
> To: cores@o...
> Date: Tue, 20 Nov 2001 22:13:16 +1100
> Subject: Re: [oc] DPLL or similar
> 
> >
> >
> > Hi Antonio,
> >
> > Antonio Olmo wrote:
> > > I would be very thanked if you can help me. Please i?m looking
> > for a
> > > several clocks for an uart. That is, i have 40 MHz clock and i
> > must
> > > get several frequencies as 24 MHz, 33 MHz,... I don?t know to
> > do a
> > > DPLL in a FPGA. Can you help me?
> >
> > Perhaps you could implement this with fractional-N dividers.  I
> > have a
> > free program that writes VHDL code for any fixed frequency
> > fractional-N
> > divider that you care to specify.  Email for a copy (remove the
> > .hates.spam part of the reply address first)
> >
> > Given that you say you are using an FPGA (which have limited clock
> > resources) and the frequency is fairly low (40MHz) I suggest having
> > everything clock from the 40MHz clock, and use clock enables on the
> > logic that you want to run at 24MHz, etc.
> > The clock enables may end up with a large fanout.  The FPGA you use
> > may
> > have buffer resources that can be used for this, or you may need to
> > fan
> > out the clock enables over a few levels of flip flops.
> >
> > Fractional-N dividers generate jitter.  You should analyse your
> > application to determine whether the amount of jitter generated is
> > acceptable.
> >
> > If you need a *variable* frequency divider, then the results of my
> > script won't be immediately useful, but you should be able to hack
> > into
> > the phase accumulator version to make it variable.
> >
> > So, can you let us know:
> >
> > Do you want the frequency dividers to be fixed (always has the same
> > output frequency), or variable (you can change the output
> > frequency)?
> >
> > What frequency accuracy do you require?
> >
> > How much jitter can your application tolerate?
> >
> > VHDL or Verilog?
> >
> > Which FPGA are you using?  (Are you aware that some FPGAs, e.g.
> > Virtex2,
> > have built-in clock synthesis?)
> >
> > Regards,
> > Allan.
> >
> --
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-- 
Allan Herriman                
Advanced Networks Division    +61 3 9210 5527 Tel
Agilent Technologies, Inc.    +61 3 9210 5550 Fax
347 Burwood Highway  Forest Hill 3131 Australia
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