[oc] NEWS-FLASH: Free VHDL to Verilog Translator

[Rudolf Usselmann <rudi@asics.ws>]

I don't know if you guys have seen this but there is a free
VHDL to Verilog translation tool that was mentioned in a
recent EEtimes article.

This is the EEtimes article:
http://www.eetasia.com/ART_8800272174_499481,499482.HTM

This is the company offering it (download page):
at www.ocean-logic.com/downloads.htm

Regards,
rudi


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