Re: [oc] Syntax errors in OCIDEC -Details

[Shehryar Shaheen <shehryar.shaheen@ul.ie>]

Try this

vcom -explicit -93 *.vhd

I also use modelsim and somtimes modelsim gives
errors other compilers don't (if some options are not used)

I havn't used this particular core but I noticed that designs
that gave no errors with VHDL Simili gave similar errors to what
you are mentioning here when compiled under modelsim.

The above command line should (hopefully) do fine

Hope this helps



----- Original Message -----
From: "Volker Urban" <volker.urban@web.de>
To: <cores@opencores.org>
Sent: Monday, September 02, 2002 7:36 PM
Subject: [oc] Syntax errors in OCIDEC -Details


> Today I got a fresh  zipped tar ball for OCIDEC and tried do find the
> mentioned errors agains. Here are the results from compiling with
modelsim:
>
>   vcom -93 *.vhd
>
> ocidec1:
> --------
> ERROR: atahost_controller.vhd(275): near "end": expecting: IF
> ERROR: atahost_controller.vhd(321): near "architecture": expecting:
PROCESS
>
> 275: missing "if;" in "end if;"
>
> ocidec2:
> --------
> ERROR: atahost_controller.vhd(300): near "end": expecting: IF
> ERROR: atahost_controller.vhd(349): near "the": expecting: GENERATE THEN
> ERROR: atahost_controller.vhd(350): near ";": expecting: GENERATE THEN
> ERROR: atahost_controller.vhd(353): near "architecture": expecting:
PROCESS
>
> 300: same as ocidec1
> 350: "if .. then" instead of "if ... the"
>
> ocidec3:
> -------
> No errors
>
>
> Best regards
>
> Volker
>
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