Mail Index

• Thread Index

• Re: [oc] scrambler/descrambler
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] scrambler/descrambler
  • From: leslie kater <lkat68@yahoo.co.uk>
• Re: [oc] Ask something
  • From: "Paulus M. Tamba" <ulus@lola.ee.itb.ac.id>
• [oc] Ask something
  • From: "Mr. BS" <22961560@students.ukdw.ac.id>
• Re: [oc] HDLC controller
  • From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
• Re: [oc] Newbie here, just introducing myself
  • From: "Richard Herveille" <Richard.Herveille@pie.nl>
• [oc] Newbie here, just introducing myself
  • From: "Richard Everett" <reverett@newtonlabs.com>
• Re: [oc] FIFO or shared memory
  • From: Steve Wilson <stevew@intrinsix.com>
• [oc] FIFO or shared memory
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] Wishbone DMA specification
  • From: "Rudolf Usselmann" <rudi@asics.ws>
• [oc] FreeProc: The Open CPU
  • From: Alan Grimes <alangrimes@starpower.net>
• RE: [oc] VHDL code for Bluetooth module
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• RE: [oc] VHDL code for Bluetooth module
  • From: "Rudolf Usselmann" <rudi@asics.ws>
• Re: [oc] Want to Join in Core Development Team
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] Want to Join in Core Development Team
  • From: Souvik Basu <souvik@cse.iitk.ac.in>
• Re: [oc] VHDL code for Bluetooth module
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Incorporation (was Re: [oc] VHDL code for Bluetooth module)
  • From: John Dalton <johnd@southern-poro.com>
• Re: [oc] New open project for a display architecture
  • From: Alan Grimes <alangrimes@starpower.net>
• [oc] New open project for a display architecture
  • From: Neo Laengerich <neo@laengerich.de>
• Re: [oc] VHDL code for Bluetooth module
  • From: Victor the Cleaner <jonathan@canuck.com>
• RE: [oc] VHDL code for Bluetooth module
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• RE: [oc] VHDL code for Bluetooth module
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• RE: [oc] VHDL code for Bluetooth module
  • From: John Dalton <john.dalton@bigfoot.com>
• [oc] New WISHBONE Models
  • From: "Winefred Washington" <wwashington@austin.rr.com>
• [oc] CAN core
  • From: "Tan, Wei (CRD, CRD)" <Wei.Tan@geahk.ge.com>
• Re: [oc] VHDL code for Bluetooth module
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] VHDL code for Bluetooth module
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] VHDL code for Bluetooth module
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] Obtain Biotech IPOs! 123
  • From: emed11@libero.it
• [oc] VHDL code for Bluetooth module
  • From: Sanat Kamal <sanatbahl@usa.net>
• Re: [oc] HDLC controller
  • From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
• Re: [oc] Is someone working on IEEE1394
  • From: Damjan Lampret <lampret@opencores.org>
• [oc] Is someone working on IEEE1394
  • From: Neo Laengerich <neo@laengerich.de>
• [oc] New version controlled archives..
  • From: Alan Grimes <alangrimes@starpower.net>
• Re: [oc] CRC core
  • From: "Igor Mohor" <igor.mohor@uni-mb.si>
• Re: [oc] CRC core
  • From: John Dalton <johnd@southern-poro.com>
• [oc] Silly SIMD cpu opcode map
  • From: tom st denis <tomstdenis@yahoo.com>
• [oc] .
  • From: sandywho1212@yahoo.com
• [oc] PowerPC-interface and VME-Core
  • From: Neo Laengerich <neo@laengerich.de>
• RE: [oc] CRC core
  • From: "Igor Mohor" <igor.mohor@uni-mb.si>
• Re: [oc] HDLC controller
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] HDLC controller
  • From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
• Re: [oc] CRC core
  • From: "Richard Herveille" <Richard.Herveille@pie.nl>
• [oc] CRC core
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] Opencores Boilerplate License
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] Opencores Boilerplate License
  • From: "Winefred Washington" <wwashington@austin.rr.com>
• Re: [oc] wishbone bus anad FIFO interface
  • From: "Wade D. Peterson" <wadep@silicore.net>
• [oc] Online simulator
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] wishbone bus anad FIFO interface
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] HDLC and WISHBONE bus
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] SoC Review UPDATE
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] SoC Review UPDATE
  • From: John Dalton <johnd@southern-poro.com>
• [oc] SoC Review UPDATE
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] HDLC controller
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• [oc] A NEW CYBERPAGE IN SPACE, FUN, FUN, FUN !!!
  • From: House Of Pleasure <HOP@newsletter.com>
• [oc] NEW CYBERPAGE IN SPACE, HAVE FUN
  • From: House of Pleasure <HOP@newsmail.com>
• [oc] New WISHBONE, rev B spec now online
  • From: "Wade D. Peterson" <wadep@silicore.net>
• Re: [oc] I2C cores
  • From: "Richard Herveille" <Richard.Herveille@pie.nl>
• Re: [oc] I2C cores
  • From: "Brian Edmonston" <brian@icoding.com>
• [oc] remove
  • From: Mao Wenjie <mwj@zjuem.zju.edu.cn>
• Re: [oc] remove
  • From: Damjan Lampret <lampret@opencores.org>
• Re: [oc] Wishbone historical perspective and a proposal totheOpenCores group
  • From: "Wade D. Peterson" <wadep@silicore.net>
• [oc] remove
  • From: Jerry English <jenglish@planetc.com>
• [oc] REMOVE
  • From: Flavio Roberto Schuler de Oliveira <schuler@nupes.cefetpr.br>
• [oc] REMOVE
  • From: Lynn.Reed@Tekmos.com
• Re: [oc] SoC bus review
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] Wishbone historical perspective and a proposal totheOpenCores group
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] remove
  • From: Jerry English <jenglish@planetc.com>
• [oc] REMOVE
  • From: "Rosimildo daSilva" <rdasilva@connecttel.com>
• Re: [oc] SoC bus review
  • From: Rainer Dorsch <rainer@rai16.informatik.uni-stuttgart.de>
• [oc] remove
  • From: "Roy Kinamon" <royk@tiogatech.com>
• Re: [oc] Wishbone historical perspective and a proposal to the OpenCores group
  • From: "Wade D. Peterson" <wadep@silicore.net>
• Re: [oc] Wishbone historical perspective and a proposal to theOpenCores group
  • From: "Wade D. Peterson" <wadep@silicore.net>
• Re: [oc] Wishbone historical perspective and a proposal to the OpenCores group
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] Wishbone historical perspective and a proposal to theOpenCores group
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] Wishbone historical perspective and a proposal to the OpenCores group
  • From: "Wade D. Peterson" <wadep@silicore.net>
• [oc] remove
  • From: Harry Mullerus <harry_mullerus@yahoo.com>
• Re: [oc] SoC bus review
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] SoC bus review
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] SoC bus review
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] I2C cores
  • From: "Richard Herveille" <Richard.Herveille@pie.nl>
• Re: [oc] Simplistic Board
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] SoC bus review
  • From: "Richard Herveille" <Richard.Herveille@pie.nl>
• [oc] Simplistic Board
  • From: dvogel@intercarve.net
• Re: [oc] SoC bus review
  • From: John Dalton <johnd@southern-poro.com>
• Re: [oc] SoC bus review
  • From: Damjan Lampret <lampret@opencores.org>
• Re: [oc] SoC bus review
  • From: John Dalton <johnd@southern-poro.com>
• Re: [oc] I'd be happy to participate and answer WISHBONErelatedquestions.
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] SoC bus review
  • From: Rudolf Usselmann <rudi@asics.ws>
• Re: [oc] I'd be happy to participate and answer WISHBONE relatedquestions.
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] I'd be happy to participate and answer WISHBONE relatedquestions.
  • From: "Wade D. Peterson" <wadep@silicore.net>
• Re: [oc] Wishbus Bus
  • From: "Wade D. Peterson" <wadep@silicore.net>
• [oc] OpenTech new release
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• Re: [oc] HDLC questions
  • From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
• [oc] modular exponentiation cores
  • From: "ahmad bagus" <ahmad_bagus@hotmail.com>
• Re: [oc] Wishbus Bus
  • From: "Winefred Washington" <wwashington@austin.rr.com>
• Re: [oc] Wishbus Bus
  • From: "Wade D. Peterson" <wadep@silicore.net>
• Re: [oc] I'd be happy to participate and answer WISHBONE relatedquestions.
  • From: Rudolf Usselmann <rudi@asics.ws>
• [oc] I'd be happy to participate and answer WISHBONE related questions.
  • From: "Wade D. Peterson" <wadep@silicore.net>
• Re: [oc] Wishbus Bus
  • From: Lior.Shtram@Flextronicssemi.com
• [oc] Wishbone Bus Questions
  • From: "Winefred Washington" <wwashington@austin.rr.com>