[oc] Wishbone historical perspective and a proposal to the OpenCores group

["Wade D. Peterson" <wadep@silicore.net>]

Hello Rudi et al.:

I took a look at your SoC bus review, and found it most interesting.  I think
you're narrowing in on a solution.  In order to address the rest of your
concerns about WISHBONE, it might be a good idea to give you some
background/motivation for this thing.  In fact, let me describe how it came
about, and end it up with a proposal to the opencores group.  I apologize in
advance for this long email, but you might find it interesting.


WISHBONE Background/motivation
------------------------------
My entire career path (since '84) has been tied to microcomputer bus
industry in one way, shape or form.  I've designed a lot of boards and chips for
microcomputer buses and related standards.  I wrote a book called The VMEbus
Handbook which is now in it's fourth edition, and present a regular seminar with
VITA called UNDERSTANDING VME64 in the US, Canada and Europe.  I also work with
VITA (the VMEbus Standards organization) as a consultant, and have done quite a
bit of intellectual property work (patent research, expert witness work, etc.)
for the VMEbus Standards Organization.

In fact, in my opinion intellectual property problems (especially patents) are
now the #1 obstacle to open standards.  For example, VMEbus was created as (and
still is) an open standard.  However, at last count we found *805* US patents
relating to VMEbus technology.  Compact PCI is newer, but is showing the same
trend.  If past behavior in the microcomputer bus industry is any indication of
future behavior, then the prevailing SoC bus will have the same problems.
Currently, there is a window of opportunity to create an open SoC bus that will:
(a) be free from patent problems and (b) garner wide
industry support.

In 1998 we (Silicore) began working on IP cores.  It soon became evident that we
needed a document that explained to customers how to connect our cores to their
cores.  At that point I had a couple of large IP core projects under my belt, so
I took it upon myself to marry 15 years of microcomputer bus experience with my
IP core experience.  The resulting document was called WISHBONE, Rev A
(preliminary).

In June 1999 we were showing at the DAC conference in New Orleans, and publicly
released WISHBONE.  On the same day (at the same show) IBM released CoreConnect.
We were, of course, very disappointed that they did that, as IBM got a lot more
press
than we did ;-).  However, at the same knew that we were on the right track.  In
fact,
we think we did a better job than IBM did.

The next month we brought WISHBONE to the VMEbus Standards Organization meeting
in Vancouver, B.C.  That organization is operated by VITA (www.vita.com), who is
an ANSI approved standards developer.  It seemed like a good fit because VITA's
charter is to promote open, microcomputer bus standards.  They've also done the
best job in the industry at protecting their open standards from intellectual
property problems by providing a variety of legal defenses.  VITA also has
infrastructure in place as an ANSI standards developer.  This is important
because disputes in their standards development can be resolved quickly
(standards are as much political documents as they are technical).  There are
also some other important things that they bring to the table, such as how to
avoid U.S. anti-trust problems and how to avoid liability problems.

By the way - the WISHBONE standard is written in a style that is almost
identical to the VMEbus IEEE 1014, IEC 821 and ANSI/VITA-1 standards.  That's
where the RULES, RECOMMENDATIONS and so forth come from in the WISHBONE
standard.

Anyway, that group was suitably impressed with the technical aspects of
WISHBONE, but so far we haven't been able to garner sufficient support to
continue with a standards effort.  I think the basic problem is that the
'traditional'
microcomputer bus people are pretty mystified at the concept of a SoC bus.
These are people and companies who make their money by selling atoms - not bits.
SoC buses don't have connectors, so the connector people weren't interested.
SoC buses don't ship as boards, so the board people weren't interested.  Ray
Alderman (the executive director at VITA) is very interested in a SoC bus, as I
believe that he shares our common vision of the future.  However, VITA isn't
proceeding because their constituency isn't demanding it.

This is where WISHBONE is today.  Silicore is currently using WISHBONE, and has
committed to develop more products using the interface.  For example, right now
we are developing a set of VMEbus bridge products.  Actually, we've found the
document very useful for internal purposes.  For example, we can hand a project
to an engineer and tell him/her to design a core to match the SINGLE READ/WRITE
cycle.  At that point the engineer has a document to work from.  The same thing
happens with our clients - they just pick the features they want out of the
standard, and we make them an IP core.  We don't spend as much time noodling out
IP core interfaces anymore.


PROPOSAL TO THE OPENCORES GROUP
-------------------------------
I propose the following to the OpenCores group:

1) Silicore would put the copyright for all WISHBONE related materials into the
public domain.  This would include the spec, website FAQ, ap notes and other
materials.
2) I would make final corrections to the spec, and publish it as 'REV B
(preliminary)'.
3) The OpenCores group would take over the stewardship for the standard.  This
would allow the group to make changes to WISHBONE as they see fit.  [I am
assuming that OpenCores has some kind voting system to make changes to things].
5) Silicore would join OpenCores to garner voting rights.
6) I would make myself available in a WISHBONE technical consultant or
leadership role.

As always - questions, comments and suggestions are welcome.

Best regards,

Wade D. Peterson
Silicore Corporation
6310 Butterworth Lane
Corcoran, MN  USA  55340
TEL: (763) 478-3567, FAX: (763) 478-3568
URL: www.silicore.net  E-MAIL: wadep@silicore.net