[oc] Wishbone Bus Questions

["Winefred Washington" <wwashington@austin.rr.com>]

While working on the testbench, I've come up with two more questions:

1. How should transactions which target non-exist addresses be trapped and
handled?
2. Should we support time limits on transactions?

Regards,
WW

----- Original Message -----
From: "Ovidiu Lupas" <olupas@opencores.org>
To: <cores@opencores.org>
Sent: Sunday, December 31, 2000 12:47 PM
Subject: Re: [oc] Wishbus Bus


> Hi all,
>
> > If you are building a PCI<->Wishbone bridge (which would be super, super
> > cool :*) you will need additional information (such as bus width) from
> > the devices that you are talking to. This should be easy and straight
> > forward to add ....
> I have started the work on a PCI target, and I would like to make from it
> a PCI - Wishbone bridge. Actually, I am waiting to see what standard bus
> will be choosed to be implemented. Meanwhile, I am working on the PCI
> side ... ;)
>
> I am writing this, so not to be others developing the same thing. It is
> better
> to spread the design efforts, to cover as much designs as possible.
>
>  Best Regards,
>       Ovidiu
>
> >
> >
> >
> > on 12/31/00 11:14, Winefred Washington at wwashington@austin.rr.com
wrote:
> > > We may need to make an additional requirement to the Wishbone spec or
> > > perhaps Silicore is already working on it.
> > >
> > > I was working on a simple testbench and here's the problem I think I
> found.
> > > A master device has to know what the bus width of the slave device is
> for
> > > the transfer to work correctly. Suppose we have a 32-bit PCI to
Wishbone
> > > device and it has to transfer data to 32-bit  and an 8-bit devices.
The
> PCI
> > > core has to change how the data is presented on the bus to match the
> data
> > > width of the slave devices. That means the PCI core has to contain
logic
> > > specific to the application which hurts reuse.
> > >
> > > One solution is to fix the data widths to 32-bits for all cores.
> > >
> > > Any comments?
> > >
> > > Did I miss something in the spec?
> > >
> > > WW
> > >
> > >
> > >
> > >
> >
>