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[cvs-checkins] or1k/or1ksim/peripheral/channels Makefile.am M ...
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[cvs-checkins] oc8051/rtl/verilog oc8051_sfr.v oc8051_int.v
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[cvs-checkins] or1k/or1ksim sim.cfg
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[cvs-checkins] spi/ ench/verilog/spi_slave_model.v ench/veril ...
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[cvs-checkins] pci/rtl/verilog pci_conf_space.v pci_delayed_s ...
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[cvs-checkins] can/bench/verilog can_testbench.v
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[cvs-checkins] can/rtl/verilog can_top.v
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[cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v ench/veril ...
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[cvs-checkins] can/rtl/verilog can_top.v
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[cvs-checkins] can/rtl/verilog can_top.v
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[cvs-checkins] can/rtl/verilog can_register.v can_register_as ...
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[cvs-checkins] can/rtl/verilog can_register.v can_register_as ...
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[cvs-checkins] can/rtl/verilog can_register_asyn_syn.v
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[cvs-checkins] can/rtl/verilog can_defines.v can_register_asy ...
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[cvs-checkins] vga_lcd/doc/src vga_core_enh.doc
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[cvs-checkins] vga_lcd/doc vga_core.pdf
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[cvs-checkins] vga_lcd/doc/src vga_core_enh.doc
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[cvs-checkins] vga_lcd/doc vga_core.pdf
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[cvs-checkins] vga_lcd/sim/rtl_sim/bin Makefile
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[cvs-checkins] vga_lcd/bench/verilog test_bench_top.v wb_b3_c ...
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[cvs-checkins] vga_lcd/rtl/verilog vga_vtim.v vga_wb_master.v ...
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[cvs-checkins] vga_lcd/bench/verilog sync_check.v test_bench_ ...
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[cvs-checkins] vga_lcd/rtl/verilog generic_dpram.v generic_sp ...
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[cvs-checkins] wb2hpi/apps/pci2dsp/rtl/verilog top.v
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[cvs-checkins] or1k/orp/orp_soc/sw/except except_test.c
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[cvs-checkins] Import
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[cvs-checkins] can/bench/verilog can_testbench.v
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[cvs-checkins] can/rtl/verilog can_top.v
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[cvs-checkins] pci/bench/verilog system.v
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[cvs-checkins] pci/rtl/verilog pci_user_constants.v pci_wb_ma ...
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[cvs-checkins] pci/apps/sw/driver spartan_drv.c fb/spartan_fb ...
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[cvs-checkins] can/rtl/verilog can_register_asyn_syn.v can_re ...
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[cvs-checkins] can/rtl/verilog can_register_syn.v
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[cvs-checkins] can/rtl/verilog can_registers.v
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[cvs-checkins] mlite/tools boot.asm
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[cvs-checkins] mlite/tools convert.c
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[cvs-checkins] mlite/vhdl reg_bank.vhd
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[cvs-checkins] mlite/vhdl pipeline.vhd
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[cvs-checkins] can/rtl/verilog can_registers.v
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[cvs-checkins] can/rtl/verilog can_top.v
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[cvs-checkins] pci/apps/crt/rtl/verilog pci_user_constants.v
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[cvs-checkins] i2c/rtl/verilog i2c_master_bit_ctrl.v
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[cvs-checkins] mlite/vhdl tbench.vhd
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[cvs-checkins] mlite/vhdl plasma.vhd
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[cvs-checkins] can/rtl/verilog can_acf.v
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[cvs-checkins] mlite/tools mlite.c
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[cvs-checkins] mlite/vhdl makefile
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[cvs-checkins] mlite/vhdl tbench.vhd
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[cvs-checkins] mlite/vhdl pipeline.vhd
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[cvs-checkins] or1k/gdb-5.0/gdb remote-or1k.c
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[cvs-checkins] or1k/gdb-5.0/gdb or1k-tdep.c
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[cvs-checkins] can/syn/libero pinedit.gcf
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[cvs-checkins] can/bench/verilog can_testbench.v
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[cvs-checkins] can/rtl/verilog can_top.v
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[cvs-checkins] can/syn/libero
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[cvs-checkins] can/rtl/verilog can_defines.v
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[cvs-checkins] can/rtl/verilog can_fifo.v
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[cvs-checkins] can/rtl/verilog can_top.v
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[cvs-checkins] can/bench/verilog can_testbench.v
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[cvs-checkins] mem_if/sim/rtl_sim/run run_sim.scr
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[cvs-checkins] Import
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[cvs-checkins] can/syn/synplicity can.prj
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[cvs-checkins] can/sim/rtl_sim/bin memory_file_list
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[cvs-checkins] can/sim/rtl_sim/run run_sim.scr
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[cvs-checkins] can/syn/synplicity can.prj
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[cvs-checkins] can/rtl/verilog can_bsp.v can_fifo.v can_top.v
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[cvs-checkins] can/rtl/verilog can_defines.v
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[cvs-checkins] can/rtl/verilog can_registers.v
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[cvs-checkins] can/bench/verilog can_testbench.v
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[cvs-checkins] i2c/rtl/verilog i2c_master_top.v
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[cvs-checkins] can/ ench/verilog/can_testbench_defines.v tl/v ...
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[cvs-checkins] can/rtl/verilog can_bsp.v
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[cvs-checkins] can/ ench/verilog/can_testbench.v ench/verilog ...
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