[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[cvs-checkins] pci/rtl/verilog pci_conf_space.v pci_delayed_s ...
CVSROOT: /home/oc/cvs
Module name: pci
Changes by: mihad 03/03/26 12:16:30
Modified files:
rtl/verilog : pci_conf_space.v pci_delayed_sync.v
pci_pcir_fifo_control.v pci_pciw_fifo_control.v
pci_pciw_pcir_fifos.v pci_sync_module.v
pci_wbr_fifo_control.v pci_wbw_fifo_control.v
pci_wbw_wbr_fifos.v synchronizer_flop.v
Log message:
Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml