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[cvs-checkins] vga_lcd/bench/verilog sync_check.v test_bench_ ...

CVSROOT:	/home/oc/cvs
Module name:	vga_lcd
Changes by:	oc	03/03/19 11:21:04

Modified files:
	bench/verilog  : sync_check.v test_bench_top.v tests.v 
	                 wb_model_defines.v 

Log message:
	Changed timing section in VGA core, changed testbench accordingly.
	Fixed bug in 'timing check' test.

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