Re: [oc] Language

[jacky.lue@philips.com]

Hi. 

Regarding to VHDL/Verilog, I have two comments as follow:

<1>VHDL can not access subblock's signal directly, but verilog can do it. 

<2>VHDL can do user define type declearation, but verilog can not.

The item<1> should be cared when you make simulation model, testbench, debugging. 

The item<2> should be cared when you make more abstract design. For example, LEON's VHDL code define a recored for AHB bus. 

In my opinion, VHDL is more close to system level than verilog. But verilog work better on backend side. Reagrding to system level design, VHDL is not good enough, let expect SystemC. :-)

Ajack