Re: [oc] Language

[Billditt@aol.com]

VHDL allows you to plug in added functionality via packages. That made for 
some
cool stuff, like signals that literally took values of colors. I like it for 
doing testbenches.

    Verilog signals are all predefined. A lot of hardware oriented engineers 
liked Verilog, as it was "simpler" than VHDL. Some liked the "C" like syntax, 
finding
VHDL to be too verbose. I had one engineer who absolutely refused to use VHDL
because it was "harder" to do a edge triggered flop. I wrote some code in 
package
that recognized negedge and posedge (obviously he wasnt a good engineer, 
rather
the bosses pet who was foisted upon me).
    
    It used to be that the package flexibility made VHDL better for 
testbenches
(could insert more abstractness in testbench areas). However, with the bolt on
DV tools such as Quickbench, Specman, etc that is no longer an issue. What I 
am
watching is acceptance of SuperLog. There are a lot of higher level 
constructs,
abstractness, etc built in (aimed at DV environment). The value of this is 
that
why other DV tools run thru PLI (slow), Superlog runs everything in one 
kernel.
The down side is that you have to have a dedicated simulator for Superlog, 
where
by the other DV tools bolt on anywhere.

    I have used both VHDL and Verilog. I like Verilog because I am used to it
(80% of my projects were Verilog), but really dont have a problem with VHDL.
I'd use it again if called upon.
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