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[cvs-checkins] ethernet/rtl/verilog eth_defines.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_defines.v
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Mon, 23 Sep 2002 17:22:53 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/09/23 17:22:52

Modified files:
	rtl/verilog    : eth_defines.v 

Log message:
	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
	core.

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