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[cvs-checkins] ethernet/rtl/verilog eth_defines.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_defines.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Wed, 4 Sep 2002 17:36:52 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/09/04 17:36:52

Modified files:
	rtl/verilog    : eth_defines.v 

Log message:
	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).
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