[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] uart16550/ ench/verilog/uart_test.v oc/CHANGES ...

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	02/07/29 20:15:19

Modified files:
	bench/verilog  : uart_test.v 
	doc            : CHANGES.txt 
	sim/rtl_sim/bin: nc.scr 

Log message:
	Reverted to include uart_defines.v file in other files again.
--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml