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[cvs-checkins] Import

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] Import
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Mon, 29 Jul 2002 12:33:20 -0100
Sender: owner-cvs-checkins@opencores.org
CVSROOT:	/home/oc/cvs
Module name:	oc8051
Changes by:	simons	02/07/29 12:33:20

Log message:
    Initial CVS import
    
    Status:
    
    Vendor Tag:	simont
    Release Tags:	rel0
    
    N oc8051/.nclaunch.dd
    N oc8051/rtl/verilog/oc8051_divide.v
    N oc8051/rtl/verilog/read.me
    N oc8051/rtl/verilog/oc8051_alu_src1_sel.v
    N oc8051/rtl/verilog/oc8051_alu_src2_sel.v
    N oc8051/rtl/verilog/oc8051_alu_src3_sel.v
    N oc8051/rtl/verilog/oc8051_comp.v
    N oc8051/rtl/verilog/oc8051_cy_select.v
    N oc8051/rtl/verilog/oc8051_decoder.v
    N oc8051/rtl/verilog/oc8051_defines.v
    N oc8051/rtl/verilog/oc8051_dptr.v
    N oc8051/rtl/verilog/oc8051_ext_addr_sel.v
    N oc8051/rtl/verilog/oc8051_fpga_top.v
    N oc8051/rtl/verilog/oc8051_immediate_sel.v
    N oc8051/rtl/verilog/oc8051_indi_addr.v
    N oc8051/rtl/verilog/oc8051_op_select.v
    N oc8051/rtl/verilog/oc8051_pc.v
    N oc8051/rtl/verilog/oc8051_b_register.v
    N oc8051/rtl/verilog/oc8051_psw.v
    N oc8051/rtl/verilog/oc8051_alu.v
    N oc8051/rtl/verilog/oc8051_ram_rd_sel.v
    N oc8051/rtl/verilog/oc8051_ram_sel.v
    N oc8051/rtl/verilog/oc8051_ram_top.v
    N oc8051/rtl/verilog/oc8051_ram_wr_sel.v
    N oc8051/rtl/verilog/oc8051_reg1.v
    N oc8051/rtl/verilog/oc8051_reg2.v
    N oc8051/rtl/verilog/oc8051_reg3.v
    N oc8051/rtl/verilog/oc8051_reg4.v
    N oc8051/rtl/verilog/oc8051_reg8.v
    N oc8051/rtl/verilog/oc8051_rom_addr_sel.v
    N oc8051/rtl/verilog/oc8051_sp.v
    N oc8051/rtl/verilog/oc8051_timescale.v
    N oc8051/rtl/verilog/oc8051_top.v
    N oc8051/rtl/verilog/oc8051_multiply.v
    N oc8051/rtl/verilog/oc8051_acc.v
    N oc8051/rtl/verilog/oc8051_tb.v
    N oc8051/rtl/verilog/oc8051_ports.v
    N oc8051/rtl/verilog/oc8051_uart.v
    N oc8051/rtl/verilog/oc8051_int.v
    N oc8051/rtl/verilog/oc8051_tc.v
    N oc8051/bench/verilog/oc8051_fpga_tb.v
    N oc8051/bench/verilog/oc8051_tb.v
    N oc8051/bench/verilog/oc8051_timescale.v
    N oc8051/sim/rtl_sim/src/negcnt.vec
    N oc8051/sim/rtl_sim/src/gcd.vec
    N oc8051/sim/rtl_sim/src/int2bin.vec
    N oc8051/sim/rtl_sim/src/cast.vec
    N oc8051/sim/rtl_sim/src/divmul.vec
    N oc8051/sim/rtl_sim/src/fib.vec
    N oc8051/sim/rtl_sim/src/sort.vec
    N oc8051/sim/rtl_sim/src/sqroot.vec
    N oc8051/sim/rtl_sim/src/testall.vec
    N oc8051/sim/rtl_sim/src/lcall.vec
    N oc8051/sim/rtl_sim/src/cast.in
    N oc8051/sim/rtl_sim/src/divmul.in
    N oc8051/sim/rtl_sim/src/fib.in
    N oc8051/sim/rtl_sim/src/gcd.in
    N oc8051/sim/rtl_sim/src/int2bin.in
    N oc8051/sim/rtl_sim/src/lcall.in
    N oc8051/sim/rtl_sim/src/negcnt.in
    N oc8051/sim/rtl_sim/src/sort.in
    N oc8051/sim/rtl_sim/src/sqroot.in
    N oc8051/sim/rtl_sim/src/testall.in
    N oc8051/sim/rtl_sim/src/oc8051_rom.in
    N oc8051/sim/rtl_sim/src/oc8051_test.vec
    N oc8051/sim/rtl_sim/src/r_bank.in
    N oc8051/sim/rtl_sim/src/serial.vec
    N oc8051/sim/rtl_sim/src/div16u.in
    N oc8051/sim/rtl_sim/src/div16u.vec
    N oc8051/sim/rtl_sim/src/xram_m.in
    N oc8051/sim/rtl_sim/src/xram_m.vec
    N oc8051/sim/rtl_sim/src/r_bank.vec
    N oc8051/sim/rtl_sim/src/counter_test.in
    N oc8051/sim/rtl_sim/src/timer_test.in
    N oc8051/sim/rtl_sim/src/timer_test.vec
    N oc8051/sim/rtl_sim/src/counter_test.vec
    N oc8051/sim/rtl_sim/src/interrupt_test.in
    N oc8051/sim/rtl_sim/src/interrupt_test.vec
    N oc8051/sim/rtl_sim/src/serial_test.vec
    N oc8051/sim/rtl_sim/src/interrupt_test.asm
    N oc8051/sim/rtl_sim/src/serial_test.in
    N oc8051/sim/rtl_sim/src/verilog/oc8051_ram.v
    N oc8051/sim/rtl_sim/src/verilog/oc8051_rom.v
    N oc8051/sim/rtl_sim/src/verilog/oc8051_rom_fpga.v
    N oc8051/sim/rtl_sim/src/verilog/oc8051_xram.v
    N oc8051/sim/rtl_sim/src/verilog/oc8051_uart_test.v
    N oc8051/sim/rtl_sim/src/verilog/oc8051_timescale.v
    N oc8051/sim/rtl_sim/out/ncprep.out
    N oc8051/sim/rtl_sim/out/ncvlog.out
    N oc8051/sim/rtl_sim/out/ncelab.out
    N oc8051/sim/rtl_sim/out/testall.out
    N oc8051/sim/rtl_sim/out/lcall.out
    N oc8051/sim/rtl_sim/out/negcnt.out
    N oc8051/sim/rtl_sim/out/gcd.out
    N oc8051/sim/rtl_sim/out/int2bin.out
    N oc8051/sim/rtl_sim/out/cast.out
    N oc8051/sim/rtl_sim/out/divmul.out
    N oc8051/sim/rtl_sim/out/fib.out
    N oc8051/sim/rtl_sim/out/sort.out
    N oc8051/sim/rtl_sim/out/sqroot.out
    N oc8051/sim/rtl_sim/out/div16u.out
    N oc8051/sim/rtl_sim/out/xrom_m.out
    N oc8051/sim/rtl_sim/out/xram_m.out
    N oc8051/sim/rtl_sim/out/timer_test.out
    N oc8051/sim/rtl_sim/out/counter_test.out
    N oc8051/sim/rtl_sim/out/timer.out
    N oc8051/sim/rtl_sim/out/interrupt_test.out
    N oc8051/sim/rtl_sim/out/serial_test.out
    N oc8051/sim/rtl_sim/out/r_bank.out
    N oc8051/sim/rtl_sim/run/make
    N oc8051/sim/rtl_sim/run/make_fpga
    N oc8051/sim/rtl_sim/run/oc8051_defines.v
    N oc8051/sim/rtl_sim/run/oc8051_timescale.v
    N oc8051/sim/rtl_sim/run/run
    N oc8051/sim/rtl_sim/run/make_verilog
    N oc8051/sim/rtl_sim/run/verilog.log
    N oc8051/syn/src/verilog/oc8051_rom.v
    N oc8051/syn/src/verilog/oc8051_ram.v
    N oc8051/syn/src/verilog/disp.v
    N oc8051/syn/src/verilog/oc8051_fpga_top.v
    N oc8051/syn/src/verilog/read.me
    N oc8051/asm/test.asm
    N oc8051/asm/lcall.asm
    N oc8051/asm/serial.asm
    N oc8051/asm/DIV16U.asm
    N oc8051/asm/timer_test.asm
    N oc8051/asm/sort.c
    N oc8051/asm/timer.asm
    N oc8051/asm/divmul.c
    N oc8051/asm/fib.c
    N oc8051/asm/gcd.c
    N oc8051/asm/int2bin.c
    N oc8051/asm/negcnt.c
    N oc8051/asm/cast.c
    N oc8051/asm/sqroot.c
    N oc8051/asm/testall.c
    N oc8051/asm/xram.c
    N oc8051/asm/xram_m.c
    N oc8051/asm/counter_test.asm
    N oc8051/asm/interrupt_test.asm
    N oc8051/asm/r_bank.asm
    N oc8051/asm/serial_test.asm
    N oc8051/asm/hex/cast.hex
    N oc8051/asm/hex/div16u.hex
    N oc8051/asm/hex/divmul.hex
    N oc8051/asm/hex/fib.hex
    N oc8051/asm/hex/gcd.hex
    N oc8051/asm/hex/int2bin.hex
    N oc8051/asm/hex/lcall.hex
    N oc8051/asm/hex/negcnt.hex
    N oc8051/asm/hex/serial.hex
    N oc8051/asm/hex/sort.hex
    N oc8051/asm/hex/sqroot.hex
    N oc8051/asm/hex/testall.hex
    N oc8051/asm/hex/timer_test.hex
    N oc8051/asm/hex/xram.hex
    N oc8051/asm/hex/xram_m.ihx
    N oc8051/asm/hex/timer.hex
    N oc8051/asm/hex/counter_test.hex
    N oc8051/asm/hex/interrupt_test.hex
    N oc8051/asm/hex/r_bank.hex
    N oc8051/asm/hex/serial_test.hex
    N oc8051/asm/in/cast.in
    N oc8051/asm/in/div16u.in
    N oc8051/asm/in/divmul.in
    N oc8051/asm/in/fib.in
    N oc8051/asm/in/gcd.in
    N oc8051/asm/in/int2bin.in
    N oc8051/asm/in/lcall.in
    N oc8051/asm/in/negcnt.in
    N oc8051/asm/in/counter_test.in
    N oc8051/asm/in/serial.in
    N oc8051/asm/in/sort.in
    N oc8051/asm/in/sqroot.in
    N oc8051/asm/in/testall.in
    N oc8051/asm/in/timer.in
    N oc8051/asm/in/timer_test.in
    N oc8051/asm/in/xram.in
    N oc8051/asm/in/xram_m.in
    N oc8051/asm/in/r_bank.in
    N oc8051/asm/in/serial_test.in
    N oc8051/asm/in/interrupt_test.in
    N oc8051/asm/vec/cast.vec
    N oc8051/asm/vec/div16u.vec
    N oc8051/asm/vec/divmul.vec
    N oc8051/asm/vec/fib.vec
    N oc8051/asm/vec/gcd.vec
    N oc8051/asm/vec/int2bin.vec
    N oc8051/asm/vec/lcall.vec
    N oc8051/asm/vec/negcnt.vec
    N oc8051/asm/vec/serial.vec
    N oc8051/asm/vec/sort.vec
    N oc8051/asm/vec/sqroot.vec
    N oc8051/asm/vec/testall.vec
    N oc8051/asm/vec/timer_test.vec
    N oc8051/asm/vec/timer.vec
    N oc8051/asm/vec/xram_m.vec
    N oc8051/asm/vec/counter_test.vec
    N oc8051/asm/vec/serial_test.vec
    N oc8051/asm/vec/interrupt_test.vec
    N oc8051/asm/vec/r_bank.vec
    N oc8051/asm/v/counter_test.v
    N oc8051/asm/v/serial_test.v
    N oc8051/asm/v/interrupt_test.v
    N oc8051/asm/v/r_bank.v
    N oc8051/asm/v/div16u.v
    N oc8051/asm/v/lcall.v
    N oc8051/asm/v/timer.v
    N oc8051/asm/v/serial.v
    N oc8051/asm/v/timer_test.v
    N oc8051/asm/v/cast.v
    N oc8051/asm/v/divmul.v
    N oc8051/asm/v/fib.v
    N oc8051/asm/v/gcd.v
    N oc8051/asm/v/int2bin.v
    N oc8051/asm/v/negcnt.v
    N oc8051/asm/v/sort.v
    N oc8051/asm/v/sqroot.v
    N oc8051/asm/v/testall.v
    N oc8051/asm/v/xram.v
    N oc8051/asm/v/xram_m.v
    
    No conflicts created by this import
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