[cvs-checkins] ethernet/bench/verilog tb_ethernet.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/07/19 13:02:48

Modified files:
	bench/verilog  : tb_ethernet.v 

Log message:
	Clock mrx_clk set to 2.5 MHz.
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