[cvs-checkins] or1k/mp3/rtl/verilog/or1200 cpu.v du.v except. ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	01/11/18 09:36:32

Modified files:
	mp3/rtl/verilog/or1200: cpu.v du.v except.v id.v ifetch.v 
	                        or1200.v 

Log message:
	For GDB changed single stepping and disabled trap exception.

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