[cvs-checkins] mem_ctrl/rtl/verilog mc_mem_if.v mc_timing.v m ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_ctrl
Changes by:	rudi	01/09/02 04:28:29

Modified files:
	rtl/verilog    : mc_mem_if.v mc_timing.v mc_top.v 

Log message:
	Many fixes for minor bugs that showed up in gate level simulations.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml