[cvs-checkins] mem_ctrl/bench/verilog test_bench_top.v test_l ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_ctrl
Changes by:	rudi	01/09/02 04:29:43

Modified files:
	bench/verilog  : test_bench_top.v test_lib.v tests.v 
	bench/verilog/160b3ver: adv_bb.v 

Log message:
	Fixed the TMS register setup to be tight and correct.

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