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Re: [oc] MPU Core vs. Coldfire etc...
Aloha!
kland@neuralog.com wrote:
> Went to a mini class on the Altera Nios core running in a Cyclone FPGA.
>
> The workflow and toolchain were phenomenal, but in seriously
> considering this approach over say our existing coldfire 5206e and 5407
> designs many questions arise.
>
> Will these mpu cores keep up with these processors in terms of
> performance? I don't see any instruction and data caches. Does that
> mean I need to use separate data and instruction SRAM busses to get
> high performance? (our arithmetic ecoding based compressiion is CPU
> intensive)
>
> I start adding up the LE's and pins required to do my design on the
> Cyclone and it escalates rapidly. (That is if I have to implement
> Harvard memory models on the two or three cpu cores I'd want in there)
>
> I see the upcoming Spartan III's have a significant amount of RAM and
> so I see the possibility of performance without (so much) external RAM.
Nios 3.0 contains (among quite a few new good things) configurable data and
instruction caches. See:
http://www.altera.com/products/devices/nios/features/nio-whatsnew.html?xy=nrn1_whn
Also, simply adding an internal RAM gives you an old-school programmable
cache. Place your RT-critical routines there (in that memory area) and you are
set.
An important issue with configurable MCUs like Nios, MicroBlaze or cores from
ARC, Tensilica etc is that you _adapt_ the CPU and _add_ peripherials needed
to meet the functionality and performance of the application. If you need 600
MFLOPs FIR performance, you probably don't won't a Nios on steroids, but a
FIR-coprocessor that might be _controlled_ by a normal 10-50 MIPS Nios.
Question: Why do you need three CPU-cores on chip? What does your data- vs
control plane look like.
Yes, if you start adding registers, barrel multiplier, caches, peripherials
the size of the MCU scales pretty rapidly, but compared to a ColdFire you
_can_ do these selections and get the minimal size needed for the application.
Also, there is the SW-side to consider. The ability to add custom
instructions, select 16- or 32-bit instruction set etc helps you keep the
SW-size down. Nios in all though have a pretty weak instruction set (compared
to ARM and to some extent MicroBlaze), which results in quite big code.
I really like the Altera SOPC and Nios. Especially with the Cyclone devices
(which has lots of memory), it's very easy to generate competitive application
adapted MCUs that beat the pants of Coldfires etc on price, functionality and
performance - especially the ability to get "just enough" performance.
> Are my fears of low performance from mpu cores missplaced or are they
> really on suitable for control? Are there any published benchmark
> scores for various cores running on various FPGA's?
Well, you seem to think in pure SW-terms where the poor CPU is supposed to do
all work. In a SoC, the processor is augumented with application specific
coprocessors and peripherials to support and offload the main processor.
Therefore you normally don't need big honkin' CPUs. Remember, do system design
with separate control and data paths. Do profiling on the application and
attack the common case/bottle neck with HW.
Altra has a good case study/methodology white paper about this. They profile
the EEMBC FIR benchmark and adds a coprocessor to a Nios. See:
http://www.altera.com/literature/wp/wp_design_method.pdf
As far as benchmarking goes, Altera have (AFAIK) released any EEMBC benchmarks
for Nios itself. However, you can probably assume somthing like just under 1
MIPS/MHz . Nios is a single scalar core after all.
I found a good article on the subject of embedded cores here:
http://www.e-insite.net/ednmag/index.asp?layout=article&articleid=CA47064
Good luck.
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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