[oc] MPU Core vs. Coldfire etc...

[kland@neuralog.com]

Went to a mini class on the Altera Nios core running in a Cyclone FPGA.  

The workflow and toolchain were phenomenal, but in seriously 
considering this approach over say our existing coldfire 5206e and 5407 
designs many questions arise.

Will these mpu cores keep up with these processors in terms of 
performance?  I don't see any instruction and data caches.  Does that 
mean I need to use separate data and instruction SRAM busses to get 
high performance? (our arithmetic ecoding based compressiion is CPU 
intensive)

I start adding up the LE's and pins required to do my design on the 
Cyclone and it escalates rapidly.  (That is if I have to implement 
Harvard memory models on the two or three cpu cores I'd want in there)

I see the upcoming Spartan III's have a significant amount of RAM and 
so I see the possibility of performance without (so much) external RAM.

I also see a lack of integrated development tools over at the xilinx. 

Are my fears of low performance from mpu cores missplaced or are they 
really on suitable for control?   Are there any published benchmark 
scores for various cores running on various FPGA's?

Is this the place to discuss these issues or is there another or am is the 
only way to get the dev boards and find out for myself.  I'd like to think 
someone has travelled this path and is willing to share some wisdom.

Thanks,
Ken
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