Re: [oc] MPU Core vs. Coldfire etc...

[kland@neuralog.com]

Joachim,

Aloha!

You sure know how to get a guy thinking!

Your reference on coprocessors or parallel threads is exactly what I'm 
thinking about.  I need about 150 MIPs worth of processing and my 
algorithms are C code.  So my coprocessors or threads would be 
additional Nios cores executing those algorithms.  

Since a simple 16bit Nios core can be had for <1000LE's why not have a 
little multi-processor fun?  (Beowolf cluster on a single chip anyone? :) 

I was worried about where these coprocessors were going to get their 
instruction and data memory from without bus contention.  I missed the 
power of the M4k blocks though.  I see now how one could use these to 
communicate among these coprocessors and never have the need to tie 
up an external bus.  In fact one could view the larger external memory 
as a bag of routines to swap in and out of M4k's as needed. 

If trips to offchip memory for instructions can be kept low enough then 
only that one large memory would be required for both instructions and 
data buffering.  (Depending on how good the caching is in the new 3.0 
core, one may not need to worry about it.)

Now if the FIFO model of the M4k's included AlmostFull and Empty flags 
it would almost be too easy to pipeline multiple Nios stages :)

I'm drooling over creating my own custom instructions and now that 
you've shown me the M4k light I can't wait to get started!

I'll have to see how many blocks M4k's are taken up per Nios core.

Thanks,
Ken


> 
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml