Re: [oc] I2C Master Core problem

[Daniel Haensse <haensse@swissembedded.com>]

Hi Matija,

check the appendix of the I2C doc, it includes some examples. 

This is a piece of code that we use in the Dragonix bootloader to set up the 
LCD contrast on MAX1621 (write cycle to a device with address 2c, followed by 
the display contrast value). 

regards

Dani

/* Set Contrast Voltage, see pdf for table */
void SetContrast(unsigned char data)
{
 writeb(65,I2C_PRERLO); // Generate a 100kHz clock
 writeb(0,I2C_PRERHI);
 writeb(0x80,I2C_CTR); // Enable core, no interrupts

 // assume that we are the only master, so we don't check the state of the bus
 writeb(0x58,I2C_TXR); // Write operation of address 2c
 writeb(0x90,I2C_CR);  // Send that start condition, followed by 7 bit address 
and write bit
 while((readb(I2C_SR)&0x02)) ; // Wait for transfer to be finished
 if((readb(I2C_SR)&0x80)) {printf("\nI2C error: slave does NAK");}
 writeb(data,I2C_TXR); // Write operation of data
 writeb(0x50,I2C_CR);  // send that byte
 while((readb(I2C_SR)&0x02)) ; // Send 8 bit of data followed by a stop 
condition
 if((readb(I2C_SR)&0x80)) {printf("\nI2C error: slave does NAK");}
}


Am Dienstag, 1. Juli 2003 14.43 schrieb matija habek:
> Hello.
> I have problems with sending data via I2C Master Core.Can somebody tell me,
>
> which registers must I initialise and which bit's in register's too, every
> step
>
> please.
> Which Wishbone signal mus I assert?How many clock cycles must I use for
> initialisation
>
> registers?Can somebody send me a example of SCF Wavewform file for
> simulation
>
> in VHDL if thats not a problem?
> Thanks.
> Regards,Matija from Croatia

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