RE: [oc] I2C Master Core problem

["Richard Herveille" <richard@asics.ws>]

Look at the testbench in the I2C directory.
It is in verilog (not VHDL), but should give you a hint on what to do.

Richard


> -----Original Message-----
> From: owner-cores@opencores.org 
> [mailto:owner-cores@opencores.org] On Behalf Of matija habek
> Sent: dinsdag 1 juli 2003 14:43
> To: cores@opencores.org
> Subject: [oc] I2C Master Core problem
> 
> 
> Hello.
> I have problems with sending data via I2C Master Core.Can 
> somebody tell me,
> 
> which registers must I initialise and which bit's in 
> register's too, every step
> 
> please.
> Which Wishbone signal mus I assert?How many clock cycles must 
> I use for initialisation
> 
> registers?Can somebody send me a example of SCF Wavewform 
> file for simulation
> 
> in VHDL if thats not a problem?
> Thanks.
> Regards,Matija from Croatia
> 
> 
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