Re: [oc] RE: Question

[Victor the Cleaner <jonathan@canuck.com>]

> If you just want to use Xilinx and not support any other vendor, this is 
> probably the simplest and fastest way to go.
> If you want to be more open; support more FPGA vendors try the following code:
> 
> //
> // Instantiate synthesizeable FPGA memory
> //
> 
> reg [dw-1 :0] mem [(1<<aw) -1:0];
> reg [dw-1 :0] do;
> 
> reg [aw-1 :0] raddr;
> 
> always@(posedge clk)
>    begin
>      // read operation
>      raddr <= #1 addr;    // read address registered to read clock
>      do <= #1 mem[raddr];
> 
>      // write operation
>     if (we)
>       mem[addr] <= #1 di;
>    end
> 
> 
> parameters
> aw : addressbus width
> de: databus width
> 
> signals
> clk: clock
> addr: read/write address
> do: data-output (from memory)
> di: data-input (towards memory)
> we: write enable
> 
> Richard

Richard:

I think you're answering the wrong question.  As I understood it, the
question was not how to synthesize the RAM, it was how to initialize
the *contents* of the RAM that's been instantiated.  Xilinx provides
about six different methods of getting initial data into the bitstream.

Jonathan

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