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Re: [oc] RE: Question

> I am currently trying to initialize some Xilinx block-RAMs in my Verilog code, using Xilinx Foundation 3.1i.
> I followed the instructions which say to use:
> 
> //synopsys attribute <name> <value>
> 
> So, I ended up adding:
> 
> //synopsys attribute dp_ram_block_1/ram0/ram0/INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF"
> 
> But it does not seem to work.  Does anyone have an example of initializing Xilinx BLOCK RAMs for FPGA Express or Xilinx FND3.1i?
> I am stuck.
> 
> - John Clayton

John:

I haven't tried initializing the Block RAM from HDL, but I have tried two
other methods:  In Coregen and via the .ucf file.

Doing it through Coregen is totally easy - you just tell it you want to
initialize the memory and specify the .mif file, which contains the data
in A Sensible Format. 

Don't get me started on doing it via the .ucf - it's total insanity.  It
can be done, but you won't like it.

This was under 3.1i, btw.

Jonathan

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