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Re: [pci] search path / include directory

To: pci@opencores.org
Subject: Re: [pci] search path / include directory
From: Nico Weling <eedniwe@eed.ericsson.se>
Date: Thu, 19 Jun 2003 09:59:16 +0200 (MEST)
Reply-To: pci@opencores.org
Sender: owner-pci@opencores.org

>Please confirm that you use Ise-5.2. At told before, 5.1 couldn't handle
>multiple directories. The error message was like you show it now.

Ups, I'm sorry. I realy used 5.1. Now after uprgading to 5.2 and installing 
service pack 3 it is still not automatically adding the files to the project.


I manually added the needed files. And this is working fine now without any 
problems.

I attached the project file and renamed it to ise-openpci-nico.npl to avoid 
mismatch. 

If someone else (Matt) could try this file and confirms that it works fine maybe 
Mihad could add it to CVS?


Regards/Nico.

PS: Step by step howto:
-download latest source package 
-untar tar xvzf pci.tar.gz
-copy ise-openpci-nico.npl to : pci/apps/crt/syn/webpack/
-double click the file in explorer and everything should be done automatically
-now you should be able to systhesize TOP.v without errors

JDF F
// Created by Project Navigator ver 1.0
PROJECT ise-openpci
DESIGN ise-openpci_uwe Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG fg456
DEVPKGTIME 1048677217
DEVSPEED -6
DEVSPEEDTIME 1048677217
FLOW XST Verilog
FLOWTIME 0
MODULE ..\..\rtl\verilog\ssvga_crtc.v
MODSTYLE ssvga_crtc Normal
MODULE ..\..\..\..\rtl\verilog\pci_wbw_wbr_fifos.v
MODSTYLE pci_wbw_wbr_fifos Normal
MODULE ..\..\..\..\rtl\verilog\pci_serr_crit.v
MODSTYLE pci_serr_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_pci_tpram.v
MODSTYLE pci_pci_tpram Normal
MODULE ..\..\..\..\rtl\verilog\pci_wbr_fifo_control.v
MODSTYLE pci_wbr_fifo_control Normal
MODULE ..\..\..\..\rtl\verilog\pci_io_mux_ad_load_crit.v
MODSTYLE pci_io_mux_ad_load_crit Normal
MODULE ..\..\..\..\rtl\verilog\meta_flop.v
MODSTYLE meta_flop Normal
MODULE ..\..\..\..\rtl\verilog\pci_perr_en_crit.v
MODSTYLE pci_perr_en_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_async_reset_flop.v
MODSTYLE pci_async_reset_flop Normal
MODULE ..\..\..\..\rtl\verilog\pci_serr_en_crit.v
MODSTYLE pci_serr_en_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_wbw_fifo_control.v
MODSTYLE pci_wbw_fifo_control Normal
MODULE ..\..\..\..\rtl\verilog\pci_parity_check.v
MODSTYLE pci_parity_check Normal
MODULE ..\..\..\..\rtl\verilog\bus_commands.v
MODSTYLE ..\..\..\..\rtl\verilog\bus_commands.v Normal
MODULE ..\..\..\..\rtl\verilog\pci_target32_interface.v
MODSTYLE pci_target32_interface Normal
MODULE ..\..\..\..\rtl\verilog\pci_master32_sm.v
MODSTYLE pci_master32_sm Normal
MODULE ..\..\..\..\rtl\verilog\pci_delayed_sync.v
MODSTYLE pci_delayed_sync Normal
MODULE ..\..\..\..\rtl\verilog\pci_target32_devs_crit.v
MODSTYLE pci_target32_devs_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_target32_sm.v
MODSTYLE pci_target32_sm Normal
MODULE ..\..\..\..\rtl\verilog\pci_frame_load_crit.v
MODSTYLE pci_frame_load_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_wb_tpram.v
MODSTYLE pci_wb_tpram Normal
MODULE ..\..\rtl\verilog\ssvga_defines.v
MODSTYLE ..\..\rtl\verilog\ssvga_defines.v Normal
MODULE ..\..\..\..\rtl\verilog\pci_target32_stop_crit.v
MODSTYLE pci_target32_stop_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_par_crit.v
MODSTYLE pci_par_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_pciw_pcir_fifos.v
MODSTYLE pci_pciw_pcir_fifos Normal
MODULE ..\..\..\..\rtl\verilog\pci_target32_trdy_crit.v
MODSTYLE pci_target32_trdy_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_ram_16x40d.v
MODSTYLE pci_ram_16x40d Normal
MODULE ..\..\..\..\rtl\verilog\pci_wb_slave.v
MODSTYLE pci_wb_slave Normal
MODULE ..\..\..\..\rtl\verilog\pci_master32_sm_if.v
MODSTYLE pci_master32_sm_if Normal
MODULE ..\..\rtl\verilog\timescale.v
MODSTYLE ..\..\rtl\verilog\timescale.v Normal
MODULE ..\..\..\..\rtl\verilog\pci_cbe_en_crit.v
MODSTYLE pci_cbe_en_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_pci_decoder.v
MODSTYLE pci_pci_decoder Normal
MODULE ..\..\rtl\verilog\ssvga_top.v
MODSTYLE ssvga_top Normal
MODULE ..\..\..\..\rtl\verilog\pci_sync_module.v
MODSTYLE pci_sync_module Normal
MODULE ..\..\..\..\rtl\verilog\pci_target_unit.v
MODSTYLE pci_target_unit Normal
MODULE ..\..\..\..\rtl\verilog\pci_cur_out_reg.v
MODSTYLE pci_cur_out_reg Normal
MODULE ..\..\..\..\rtl\verilog\pci_mas_ad_en_crit.v
MODSTYLE pci_mas_ad_en_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_wb_addr_mux.v
MODSTYLE pci_wb_addr_mux Normal
MODULE ..\..\rtl\verilog\crtc_iob.v
MODSTYLE CRTC_IOB Normal
MODULE ..\..\rtl\verilog\ssvga_wbm_if.v
MODSTYLE ssvga_wbm_if Normal
MODULE ..\..\..\..\rtl\verilog\pci_frame_crit.v
MODSTYLE pci_frame_crit Normal
MODULE ..\..\rtl\verilog\ssvga_wbs_if.v
MODSTYLE ssvga_wbs_if Normal
MODULE ..\..\..\..\rtl\verilog\pci_conf_space.v
MODSTYLE pci_conf_space Normal
MODULE ..\..\..\..\rtl\verilog\pci_out_reg.v
MODSTYLE pci_out_reg Normal
MODULE ..\..\..\..\rtl\verilog\pci_rst_int.v
MODSTYLE pci_rst_int Normal
MODULE ..\..\..\..\rtl\verilog\pci_conf_cyc_addr_dec.v
MODSTYLE pci_conf_cyc_addr_dec Normal
MODULE ..\..\..\..\rtl\verilog\pci_wb_decoder.v
MODSTYLE pci_wb_decoder Normal
MODULE ..\..\..\..\rtl\verilog\pci_io_mux_ad_en_crit.v
MODSTYLE pci_io_mux_ad_en_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_in_reg.v
MODSTYLE pci_in_reg Normal
MODULE ..\..\..\..\rtl\verilog\pci_pcir_fifo_control.v
MODSTYLE pci_pcir_fifo_control Normal
MODULE ..\..\..\..\rtl\verilog\pci_pciw_fifo_control.v
MODSTYLE pci_pciw_fifo_control Normal
MODULE ..\..\..\..\rtl\verilog\pci_io_mux.v
MODSTYLE pci_io_mux Normal
MODULE ..\..\..\..\rtl\verilog\pci_frame_en_crit.v
MODSTYLE pci_frame_en_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_delayed_write_reg.v
MODSTYLE pci_delayed_write_reg Normal
MODULE ..\..\..\..\rtl\verilog\pci_mas_ch_state_crit.v
MODSTYLE pci_mas_ch_state_crit Normal
MODULE ..\..\rtl\verilog\pci_user_constants.v
MODSTYLE ..\..\rtl\verilog\pci_user_constants.v Normal
MODULE ..\..\..\..\rtl\verilog\pci_irdy_out_crit.v
MODSTYLE pci_irdy_out_crit Normal
MODULE ..\..\..\..\rtl\verilog\synchronizer_flop.v
MODSTYLE synchronizer_flop Normal
MODULE ..\..\..\..\rtl\verilog\pci_mas_ad_load_crit.v
MODSTYLE pci_mas_ad_load_crit Normal
MODULE ..\..\..\..\rtl\verilog\pci_wb_slave_unit.v
MODSTYLE pci_wb_slave_unit Normal
MODULE ..\..\..\..\rtl\verilog\pci_bridge32.v
MODSTYLE pci_bridge32 Normal
MODULE ..\..\rtl\verilog\ssvga_fifo.v
MODSTYLE ssvga_fifo Normal
MODULE ..\..\..\..\rtl\verilog\pci_wb_master.v
MODSTYLE pci_wb_master Normal
MODULE ..\..\rtl\verilog\top.v
MODSTYLE TOP Normal
MODULE ..\..\..\..\rtl\verilog\pci_target32_clk_en.v
MODSTYLE pci_target32_clk_en Normal
MODULE ..\..\..\..\rtl\verilog\pci_perr_crit.v
MODSTYLE pci_perr_crit Normal
DEPASSOC TOP pci_crt.ucf Normal
[Normal]
p_xstVeriIncludeDir=xstvlg, spartan2, Schematic.t_synthesize, 1048675664, "..\..\rtl\verilog ..\..\..\..\rtl\verilog"
p_xstVeriSearchPath=xstvlg, spartan2, Schematic.t_synthesize, 1056065613, "..\..\rtl\verilog ..\..\..\..\rtl\verilog"
[STATUS-ALL]
..\..\..\..\rtl\verilog\bus_commands.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\bus_commands.v.ngcFile=ERRORS,1056066326
..\..\..\..\rtl\verilog\meta_flop.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_async_reset_flop.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_bridge32.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_cbe_en_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_conf_space.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_cur_out_reg.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_delayed_sync.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_delayed_write_reg.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_frame_en_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_frame_load_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_io_mux.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_io_mux_ad_en_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_io_mux_ad_load_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_irdy_out_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_master32_sm.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_master32_sm_if.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_mas_ad_load_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_mas_ch_state_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_parity_check.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_pcir_fifo_control.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_pciw_fifo_control.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_pciw_pcir_fifos.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_pci_tpram.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_perr_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_perr_en_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_serr_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_serr_en_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_sync_module.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_target32_sm.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_target32_stop_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_target32_trdy_crit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_target_unit.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_wbr_fifo_control.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_wbw_fifo_control.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_wbw_wbr_fifos.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_wb_addr_mux.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_wb_decoder.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_wb_master.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\pci_wb_slave.v.jhdFile=WARNINGS,1056066326
..\..\..\..\rtl\verilog\synchronizer_flop.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\pci_user_constants.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\ssvga_crtc.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\ssvga_defines.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\ssvga_fifo.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\ssvga_top.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\ssvga_wbm_if.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\ssvga_wbs_if.v.jhdFile=WARNINGS,1056066326
..\..\rtl\verilog\timescale.v.jhdFile=WARNINGS,1056066326
[STRATEGY-LIST]
Normal=True

Follow-Ups:
- RE: [pci] search path / include directory
  - From: "Matt Schulte" <matts@commtech-fastcom.com>
- Re: [pci] search path / include directory
  - From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>

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