RE: [pci] 66Mhz

[<flex2@opencores.org>]

Hi!

You must understan, that the PCI bridge + CRT work in a 150k Spartan
at 33MHz. 
The same two cores were compiled for Virtex II just for test if we
can meet 66 MHz. The implementation is not optimized and the tool
usually occupies more space if the FPGA is larger and we used BLOCK
RAMs used in Spartan II or Virtex, but this was compiled for Virtex II
and the tool put warnings for all that BLOCK RAMs, that they are not
optimized for Virtex II and that 70 % of BLOBK RAMs are unused (a waste).

What is about yours 64-bit PCI (LGPL)?

Regards, Tadej


On 9/27/2002, "J.D. Bakker" <bakker@thorgal.et.tudelft.nl> wrote:

>>Hi!
>>
>>First I will answer to your question. I synthesised and implemented the
>>PCI bridge with CRT core in Virtex II -6 speed grade (xc2v1000-bg575-6)
>>without any mayor optimisations and without synthesis constraints. I used
>>the ISE 4.2 tool and it managed to meet all timings on input and output
>>pins, while PCI clock was 86 MHz and the WISHBONE clock was 97 MHz. Both
>>cores together occupied cca 31% of FPGA.
>
>So the PCI+CRT cores take 31% of a 1 million gate FPGA ?? I didn't
>realize the cores were *that* large...
>
>JDB
>[who had been planning to do PCI+(modified)CRT in a 200k gates Spartan II]
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